Any Chance of a Teensy ++ 3.1?

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The low cost board will have 60K flash (4K will be reserved for EEPROM emulation). Sorry Steve, but trade-offs had to be made to keep the cost low. We're absolutely locked into 60K at this point in time.

Overall, I think it's going to be a great product. Today there are a lot of low-cost dev boards featuring the ATTINY chips, which are terribly feature poor. The intention of is to offer a LOT more capability "for only a little more $$" than boards like Adafruit Trinket & Gemma and Chinese clones of Arduino Nano & Leonardo. It will have good USB performance (DMA-based) and still a rich peripheral set (3 serial, I2C, SPI, 10 PWM, many ADC pins, etc) and enough memory to allow for excellent compatibility with nearly all Arduino libraries.

You can't have everything on the cheaper low-end product. 5V tolerance, large memory, and CPU speed will be the main differences.
 
well, a low cost board WITHOUT the <expletive> (Harvard) dual address space and bank-switching of the PIC/AVR will be great.

Keep an eye to the competition...
$29 but to some, that's not cheap http://www.mikroe.com/mini/stm32/ 1MB flash, large RAM. Form factor is larger of course. Design 2yrs old. (just bare metal, not much usable in libraries and Mikroe's compilers are not so hot).
http://www.mouser.com/ProductDetail/mikroElektronika/MIKROE-1367/?qs=PTWijy4SnDFg2IeD44rscw== (Mouser's mark-up is probably 30% or more)
 
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PaulStoffregen said:
The low cost board will have 60K flash (4K will be reserved for EEPROM emulation).
It will have good USB performance (DMA-based) and still a rich peripheral set (3 serial, I2C, SPI, 10 PWM, many ADC pins, etc) and enough memory to allow for excellent compatibility with nearly all Arduino libraries.
Click to expand...

That sounds pretty good. I did look at ATTINY and yes, inexpensive but very feature poor plus library support is patchy at best. Wide library support at launch will probably be very important. Libraries do have a lot of __MK20DX256__ and __MK20DX128__ tests, but some of that code might work anyway with an additional elif.

For SPI peripherals which have to be monitored constantly but only reacted to occasionally (when certain events happen) or which produce a small volume of derived data (last 100ms running average, etc) one of theese could talk over I2C to a T3.x master controller thus freeing up the main T3.x SPI bus more more important tasks. A few "helper" examples would be good to develop during the beta phase, I suspect.

Potential product names: Itsy, Bitsy, Weensy, Polka, Dot.
 
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(fails to find 3 UART devices, then realizes that UART and low-power UART are counted separately)
 
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I notice MKL26Z64VFM4 has 64k Flash, 8k SRAM, I2C, SPI, 2 UART+1 low power UART, 16bit ADC w/13ENOB, 12-bit DAC :D (whee!) and, oddly, I2S :confused:. Potentially, 2 useable I2C channels. One and a half SPI :rolleyes:

QFN32 and 48Mhz. So it could potentially be T3.1 pinout compatible, right down to DAC/A14 on the end.
 
A dedicated "debug" LED (red color) which lights when an exception (e.g. bus fault) occurs would be fine. It could be used for debugging too.
Or, it could be a nice "playground" with two LEDs on board :)
 
Frank B said:
A dedicated "debug" LED (red color) which lights when an exception (e.g. bus fault) occurs would be fine.
Click to expand...

You can have this right now, with just a little bit of hacking, and of course connecting a LED and resistor.

Edit mk20dx128.c, around line 54.

Code: 
void fault_isr(void)
{
        while (1) {
                // keep polling some communication while in fault
                // mode, so we don't completely die.
                if (SIM_SCGC4 & SIM_SCGC4_USBOTG) usb_isr();
                if (SIM_SCGC4 & SIM_SCGC4_UART0) uart0_status_isr();
                if (SIM_SCGC4 & SIM_SCGC4_UART1) uart1_status_isr();
                if (SIM_SCGC4 & SIM_SCGC4_UART2) uart2_status_isr();
        }
}

Just add a line before that while() loop to turn your LED on. Easy!
 
PaulStoffregen said:
Maybe it's time to share (or "leak") a few Teensy++ 3.x details, even though the product is still pretty much in the planning phase.

Here are 5 things that are absolutely certain about Teensy++ 3.x:

  1. ARM Cortex-M4F (Floating Point Unit)
  2. Under $30
  3. More I/O pins
  4. More serial & SPI ports
  5. More memory
Click to expand...

Does more memory mean more RAM ? How much ?

I ask because decoding aac-HE (aac+) needs ~100 KB RAM :)
 
If for example the Teensy++ 3.x were to use the MK22FX512VLH12 or MK22FN1M0VLH12 then it would have 128k SRAM (and 512k or 1M Flash). Those are 64 LQFP parts.
 
Intended as a point of comparison only - hoping to not trigger a my-ARM-is-best scuffle...

From a competitive marketplace viewpoint, hardware alone, MapleLeaf Mini was good for its day, and the current Mikroe ST mini-M4 board is a good value (Mikroe's software not viable).

Not so much the board, but the chip's peripherals and H/W FPU are appealing.
Lots of goodies for the price.
But for teensy to make a change from Freescale now would likely be a lot of work.
Still, this $30 board with STM32F415RG is impressive - and would be moreso if designed/sold by other than Mikroe.

http://microcontrollershop.com/product_info.php?products_id=5403
http://www.mikroe.com/mini/stm32/


Key Features

  • Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
  • Memories
  • Up to 1 Mbyte of Flash memory
  • Up to 192+4 Kbytes of SRAM including 64-Kbyte of CCM (core coupled memory) data RAM
  • Flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories
  • LCD parallel interface, 8080/6800 modes
  • Clock, reset and supply management
  • 1.8 V to 3.6 V application supply and I/Os
  • POR, PDR, PVD and BOR
  • 4-to-26 MHz crystal oscillator
  • Internal 16 MHz factory-trimmed RC (1% accuracy)
  • 32 kHz oscillator for RTC with calibration
  • Internal 32 kHz RC with calibration
  • Sleep, Stop and Standby modes
  • VBATsupply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM
  • 3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
  • 2×12-bit D/A converters
  • General-purpose DMA: 16-stream DMA controller with FIFOs and burst support
  • Up to 17 timers: up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
  • Debug mode
  • Serial wire debug (SWD) & JTAG interfaces
  • Cortex-M4 Embedded Trace Macrocell™
  • Up to 140 I/O ports with interrupt capability
  • Up to 136 fast I/Os up to 84 MHz
  • Up to 138 5 V-tolerant I/Os
  • Up to 15 communication interfaces
  • Up to 3 × I2C interfaces (SMBus/PMBus)
  • Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control)
  • Up to 3 SPIs (42 Mbits/s), 2 with muxed full-duplex I2S to achieve audio class accuracy via internal audio PLL or external clock
  • 2 × CAN interfaces (2.0B Active)
  • SDIO interface
  • Advanced connectivity
  • USB 2.0 full-speed device/host/OTG controller with on-chip PHY
  • USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI
  • 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII
  • 8- to 14-bit parallel camera interface up to 54 Mbytes/s
  • Cryptographic acceleration: hardware acceleration for AES 128, 192, 256, Triple DES, HASH (MD5, SHA-1), and HMAC
  • True random number generator
  • CRC calculation unit
  • 96-bit unique ID
  • RTC: subsecond accuracy, hardware calendar

Lists like the above, for the practical-sized chip package on a small board, list more peripherals than can be simultaneously used. But the inventory and flexibility is key.
 
Thats not so much more than some kinetis devices.
Take a look at K64 for example (i like the SDHC interface).
K64 is available with QFP too.
 
K64.. I have looked at it - but I assume from prior posts that this sophistication isn't on the teensy product map.

I need the 64KB or more RAM, fast 8+ channel 12 bit ADCs at 32Ksps, 2+ SPI interfaces, some way to do serial protocol LEDs without CPU hogging. And with a proper modest packet radio such as the RFM69 and RadioHead, over the air reprogramming with/without an SPI flash chip memory is a must have.

This is a well funded commercial project - but quantities are only about 300 in the next 6-12 months, more in ramp-up.
 
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Frank B said:
Thats not so much more than some kinetis devices.
Take a look at K64 for example (i like the SDHC interface).
K64 is available with QFP too.
Click to expand...

Yes, K64 is available in any size from 100 to 144 pins. Thus, as we know that Teensy++ 3.x will be a 48-dip with the 28 pins closest to the USB same as Teensy 3.1, clearly it is not using a 100-pin chip when Teensy 3.1 uses a 64LQFP.

This is why I thought a K22_120 was the only reasonable choice here (from the models on Freescale's site. Unless Paul is waiting for some new chip to exit from the murk of NDA land)
 
Speculation aid

Summarising what we know from what Paul has said in this thread (in green) and what seems likely to me based on the spec sheets for the likely chips and the functions exposed on their 64-pin (++) and 48-pin (--) versions (in amber).
speculation.png
 
I didn't see in the data sheet if the package 64 LQFP has two SPI ports to map for simultaneous use. Anyone know?

Nantonos... thanks much for the great table.
 
I had checked and it does, which is why I put two SPI in the table for the ++. I believe Paul also confirmed that there will be dual SPI (complete sets of SPI, not "one and a half" SPI like on the chip used on Teensy 3.1).

I found it hard to keep track of info scattered over the thread so jotted down a table. And having done so, might as well share it. Note that the chip choices are unconfirmed, so if either product uses a different chip the speculative items may be way off.
 
Great... so you might edit the table to say that the peripherals listed are for the 64 pin version of the K22.
The data sheets these days say "up to xxx" for everything and the prospective buyer has to pore over way too much detail to find out the "does have" instead of "up to".
 
stevech said:
Great... so you might edit the table to say that the peripherals listed are for the 64 pin version of the K22.
The data sheets these days say "up to xxx" for everything and the prospective buyer has to pore over way too much detail to find out the "does have" instead of "up to".
Click to expand...
When Paul first began hinting about Teensy 3.1++, he said that the chip had not been announced yet, and he couldn't be too specific without breaking the terms of the NDA. I don't know if the chip that he intended to use has been announced since then (in which case we can intuit features from the datasheet), or if it still hasn't been announced (in which case, we are still guessing).
 
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