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kam42
02-18-2014, 06:15 PM
Hi Paul,

Haven't seen this anywhere else yet - but I'm looking through Teensyduino 1.18 rc3 and don't see register definitions for the PDB triggering of ADC1. From page 757 of the K20 reference manual. If these definitions are already in your register definitions somewhere, could you point me in the right direction?


#define PDB0_CH1C1 *(volatile uint32_t *)0x40036038 // PDB0 Channel 1 Control Register
#define PDB0_CH1S *(volatile uint32_t *)0x4003603C // PDB0 Channel 1 Status Register
#define PDB0_CH1DLY0 *(volatile uint32_t *)0x40036040 // PDB0 Channel 1 Delay 0 Register
#define PDB0_CH1DLY1 *(volatile uint32_t *)0x40036044 // PDB0 Channel 1 Delay 1 Register

Additionally, I had some initial confusion with my understanding of the comments in mk20dx128.h in \hardware\teensy\cores\teensy3\. Would the following comment changes be acceptable to make it clear that the register corresponds with channel 0?


#define PDB0_CH0C1 *(volatile uint32_t *)0x40036010 // Channel n Control Register 1
#define PDB0_CH0S *(volatile uint32_t *)0x40036014 // Channel n Status Register
#define PDB0_CH0DLY0 *(volatile uint32_t *)0x40036018 // Channel n Delay 0 Register
#define PDB0_CH0DLY1 *(volatile uint32_t *)0x4003601C // Channel n Delay 1 Register

Changed to:


#define PDB0_CH0C1 *(volatile uint32_t *)0x40036010 // Channel 0 Control Register 1
#define PDB0_CH0S *(volatile uint32_t *)0x40036014 // Channel 0 Status Register
#define PDB0_CH0DLY0 *(volatile uint32_t *)0x40036018 // Channel 0 Delay 0 Register
#define PDB0_CH0DLY1 *(volatile uint32_t *)0x4003601C // Channel 0 Delay 1 Register

PaulStoffregen
06-17-2015, 11:24 PM
I've added these.

kam42
06-18-2015, 12:12 AM
Thank you, Paul!