We want to configure Teensy Audio board as master for 8 KHz sample rate with our custom board .
In our environment,
First Scenario - Asynchronous System Main Clock
SYS_FS = 48 KHz , RATE_MODE = 0x3 (1/6 of SYS_FS rate)
provided System main clock = 12 MHz,
SCLKFREQ = 32Fs,
PLL used with integer divisor and fractional divisor equal to 16 and 786 respectively.
With this configuration , bit-clock value is equal to 512 KHz and Sample Clock(LR clock) is 16 KHz.
As mentioned in the datasheet , sample clock value should be 8 KHz .
Second Scenario - Synchronous System Main Clock
SYS_FS = 48 KHz , RATE_MODE = 0x1 (1/2 of SYS_FS rate),
provided System Main Clock = 2.048 MHz,
SCLKFREQ = 32 Fs,
PLL not used,
With this configuration , bit clock I am getting around 256 KHz and Sample Clock(LR clock) is 8 KHz .
From this Datasheet ,
SYS_FS / RATE_MODE = Fs (Sampling Frequency)
Is there anything I am missing here or else what are the required steps to configure sample clock equal to 8 KHz in master mode ??
- Pinkesh
In our environment,
First Scenario - Asynchronous System Main Clock
SYS_FS = 48 KHz , RATE_MODE = 0x3 (1/6 of SYS_FS rate)
provided System main clock = 12 MHz,
SCLKFREQ = 32Fs,
PLL used with integer divisor and fractional divisor equal to 16 and 786 respectively.
With this configuration , bit-clock value is equal to 512 KHz and Sample Clock(LR clock) is 16 KHz.
As mentioned in the datasheet , sample clock value should be 8 KHz .
Second Scenario - Synchronous System Main Clock
SYS_FS = 48 KHz , RATE_MODE = 0x1 (1/2 of SYS_FS rate),
provided System Main Clock = 2.048 MHz,
SCLKFREQ = 32 Fs,
PLL not used,
With this configuration , bit clock I am getting around 256 KHz and Sample Clock(LR clock) is 8 KHz .
From this Datasheet ,
SYS_FS / RATE_MODE = Fs (Sampling Frequency)
Is there anything I am missing here or else what are the required steps to configure sample clock equal to 8 KHz in master mode ??
- Pinkesh