Teensy 3,6: VREG_OUT to VDD (?) and choosing the clock frequency via the IDE

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mcc

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Hi,

a friend of mine has taken a look to the data sheet and reference manual of the MK66FX1M0D18
and the schematics of the board and asked me two question which I cannot find a valid answer.

1) Schematics of the Teensy 3.6: "Why is VREG_OUT _and_ the LP38691 both connected to VDD -
didn't that imply, that two regulators (the LP... and the regulator VREG_OUT) would push/pull both
on VDD? Where can I find informations on using VREG_OUT in the documentation of the processor?

2) General: "How can it be, that the clock frequency can be choosen via the IDE? Normally the IDE
is used to select, what one _have_ and there is no selector of that kind?"

*) "IDE" => Arduino IDE

I myself has tried to answer the questions via the datasheet and the reference manual -- but I didn't find sufficient ones...

How can I answer the questions ?

Thanks a lot for any help in advance!
Cheers!
Meino
 
The USB transceiver is connected to VREG_OUT. It needs 3.3V applied even when the on-chip regulator isn't used.

The chip uses a PLL and programmable dividers to generate the clocks. It's very configurable. Look at the MCG chapter for details.
 
Hi Paul,

...you dont sleep at all, aren't you ? :) :) :)

Thank you very much for your help on a SUNDAY MORING! :)

Will copy you help to my friend. I myself will take a deep look into
the reference-/datasheet.

Have a nice sunday! :)
Cheers!
Meino

EDIT: Corrected one sentence
 
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