Cyphage

I will try CCM_CCGR7 &= ~CCM_CCGR7_FLEXSPI2(CCM_CCGR_ON); Hope that wasn't part of the issue... I measured FlexSPI2 at 132.9 MHz, so PLL3 PFD0 must have been initialized earlier to 664 MHz, though I can’t find where in the code this happens...

Hello, I'm investigating a stability issue with a Teensy 4.1 used on a MicroDexed baseboard. The system is configured to run at 132.92 MHz from PLL3 PFD0 (664.62 MHz). CCM_CCGR7 |= CCM_CCGR7_FLEXSPI2(CCM_CCGR_OFF); CCM_CBCMR = (CCM_CBCMR &...