DrItanium

So I have been using a Teensy 4.1 for well over a year now to act as the chipset for an i960 and have come up with what I would like to see in a teensy 4.2. Note, that I totally understand if some of these are unfeasible. All of these changes use...

Good to know, thank you! EDIT: I was able to get the transaction detector to free up the physical pin :)

Individual pin mux doesn't need to be set to FlexIO unless you want it to read/drive that physical pin, the FlexIO state register is the internal state.

I am currently using FlexIO1 and FlexIO2 in state machine mode to detect various aspects of the i960Sx memory transaction (using a teensy 4.1). FlexIO1 is used to identify when the i960Sx goes into a memory transaction. FlexIO2 is used to convert...

If it's a receiver it should use input mode. Shifter 1 will have to use 8-bit width in order to control direction of all 8 lines. I would consider changing your pin definitions so the data pins are on FlexIO 0-7, so their direction can be...

Yes. The main problem is there's only a couple of shifters that can do parallel output to IOs (width >1) so using state mode is almost always necessary if you want to use both bidrectional output data and bidirection output enable.

Ah, I see. So it really is smart to rearrange the data lines to be the lowest 8 flexio pins. I will put this on hold for now and redesign the interface PCB first. Thank you!

That is really helpful thanks :). I can't change those pin definitions right now without redesigning the interface PCB but I will make a note to do that when I go to make a new spin of the interface PCB. I am assuming that you would configure...

I'm trying to emulate a simple EBI/SMI interface using FlexIO3 on a teensy 4.1 so I can offload the timing requirements of communicating with two CH351 in 32-bit io expander mode (It uses a simple parallel bus design). I am doing this so I can...

I just realized that the link is now broken since I refactored code. Here is a permalink: https://github.com/DrItanium/SxChipset_V3/blob/3b41dcc2155bb10b0d06368ec21b50e76580e01d/projects/Chipset/src/FlexIOImpls.cc#L31

I am using a teensy 4.1 to act as the "Chipset" and memory interface for an Intel i960SB-16 (running at 12MHz). It is combined with an AVR128DB64 for extended strict timing functionality (CCLs are wonderful). Anyway, I have FlexIO1 and FlexIO2...