DrM

So... I'm getting ready to actually try this. Re-reading the PWM, I think it might actually be possible to setup the clocks I need and start them with sufficiently low latency. So I am eager to try that. Re-reading the LPSPI, there seems to...

Yes, that is one of the things I like about it. If I can figure out, or someone can offer, how to run the SPI from it, it would be fantastic. This how a lot of ADC's work nowadays. So it would be a hugely useful capability and very worthy of...

Thank you for the discussion so far though, it has been helpful. With that and re-reading the PWM a few times, I am starting to get it.

Well naively, the PWM could clock the readout, the output pulse would be the assertion of the CS (CNVST) for 700nsec, and then on the trailing edge it could start the SPI. But it would have to be a hardware mechanism (rather than an ISR) that...

Yes, I agree, generally. The CNVST pin happens to be the CS (pin 10) from the SPI interface. And according to this, it is not a flexPWM pin. Hence the question about rerouting the pins. Is that something the XBAR can do? (Is there a...

As presently coded, I can't have any code run whether from an interrupt or anything else, during the readout. Following is the readout. This gets luanched on the falling edge of the "C" output described above. Notice that it syncs itself to...

Thank you. The problem is that I can't run an ISR during the readout. It will mess up the timing. But now, after finally starting to grok the PWM section in the RM, a bit, it seems like a good solution might be to use three PWM modules. Is it...

I forgot to mention something. In the application, the code that generates B and C (and the readout) is launched in one of three ways: (a) on user command, (b) on a timer interrupt (the user commanded to read the ccd every so many second) or...

I see. The challenge that I am trying to solve, is to keep A and B running accurately, while I am running a loop in software. Here is the context a little more specifically. It is about a linear CCD. The first clock A, is the master clock...

There is no timing requirement between A and the other two clocks. For the 100msec interval between B pulses, the B pulse width can be a bit more than 1usec, for example 2usec or even a few usec. That brings it into the range of 15 bits C...

I want to output three clocks, A, B and C as follows A on pin 4 (or 5), a simple 50% square wave, 2MHz B on pin 8, is a 1usec pulse, every "n" microseconds (in the range 100usecs to 100msecs). C on pin 7, is a 2usec pulse, every M-th B...

is there a high level document that explains all of that? I see you have the usual oxygen sort of documentation. But to understand even that, I would still need to invest in a detailed study of the FlexPWM in the RM.

Hi, is there an API that supports using the ability of the FlexPWM to generate interrupts? I see there are at least two threads that describe doing this using register access, from about two years ago. The question is, has this capability...

1( The kicad files are in whatever version was current when it was designed. When kicad is at 20, that release will still be at 6. Else it would be a new release. I don't think you expect the design files to update themselves while they sit...

BTW it works pretty well. But, I am updating the boards and adding more, so now is a good time to be helpful.

@bicycleguy I am happy to hear constructive criticism. My experience is that this is a better forum for it. What would you like to offer?

Yes, that is typical. Their MCP33131D datasheet makes it explicit. The arduino class boards and/or their spi implementations, are not very consistent about what happens with the MISO line between packets. Add to that, that the arduino...

The Teensy4x Pins mux shows UART1 TX, RX as pins 24 and 25. So that would seem to explain what is reported in the thread referenced by @h4yn0nnym0u5e It is easy enough to avoid those if that is all there is. Again, the state of the pins...

Great, thank you. Perfect. In other words the pins are in their default state when the "sketch" is entered. I'll look again, my first impression was that they are tri-stated. In other words, a peripheral that powers up ahead of the Teensy...

It is hard to generalize, but for the circuits that I build, I don't think I would stack above or below an MCU board, unless there was really very good shielding and very good power filtering. The best thing is make a PCB with a footprint for...

P.P.S. re the lm386, etc, I dont want to say "do this" or that, but nowadays i almost always use spice, and include noise and response analyses, before I build the circuit

The 3.3V line is produced by an LDO, a TLV75733P The design process normally would be that you formulate a noise budget at various points in your circuit, check the data sheet for the noise level from the LDO, and check the power supply...

Paul doesn't have to post the code to answer the question. Does the bootloader configure the pins? Or does it leave them tri-stated? Or, some of them? It is certainly something that we need to know if we are designing a power-up involving...

@PaulStoffregen Paul, does your boot prom configure or put the dio pins in any particular state? If we had the source code for the boot prom we could check this ourselves. It is a very important thing to know.

@jmarsh Thank you, perfect. That is indeed exactly what I was looking for. But now that I see Paul's library, some other uses come to mind, For example, a temperature control loop with a thermistor and a TEC powered by a programmable power...

@SmashedTransistors Ahhh, those clever americans! The USB host on the T4.1 is powered through a TPD3S014 (a current limit switch) and the enable is controlled by the MCU. It does everything you need, over and reverse current, and...

So, at last, something like an answer from NXP. It turns out that the 30MHz limit is empirical. They tested it over some range of conditions and determine that this is the fastest speed at which remained reliable over that set of test...