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    • R
      Thanks I will try adding the 0.1uF capacitors! The existing decoupling 10uF caps are approx. 2.5mm from the pin. PCB traces on the isolated gnd side are 10mils / 0.254mm wide, would that qualify as skinny? In my understanding this should be ok...
    • R
      A few things to try... Replace the 10uF capacitors with the recommended 0.1uF capacitors. 10uF has too high an ESR rating to be useful. Or, place a 0.1uF capacitor in parallel with the 10uF. Did you place the isolator Vcc decoupling capacitors...
    • R
      I didn't think about propagation delay from the isolator, thank you for your input! I will consider this in the next iteration of the design, and try bypassing the isolator for now. Propagation delay however would just affect the timing of my SPI...
    • R
      Yes. But the propagation delay is up to 66ns. If your clock goes through the buffer and then the data comes back through the buffer then that gives you a worst case of 132ns between the clock edge and the data being ready. Assuming an instant...
    • R
      Thank you. One output line from the ISO7340 is carrying the isolated "manual" SCLK from the Teensy and going directly to the SCLK input of all four ADCs. I considered it might be a load matter but total capacitance should be around 40pF so...
    • R
      So, All 4 ADCs need SCLK, I assume they are coupled? are they using one isolater each or one for all pins. Could it be a "load" matter? I did only a brief scan of the datasheets. But I can not see the exact diagram how yuo coupled the SCLK to...
    • R
      With manual control of the pins - not the SPI hardware ? - look into setting the slew rate higher for faster rise time?
    • R
      Thanks! Yes I need to use manual controls so I can read the data from 4 ADCs at the same time. Basically the same "manual" SPI read instruction will feature reading and storing incoming bits from four lines. Would changing the Teensy slew rate...
    • R
      Hi everyone, for a university project I am trying to implement simultaneous readout from multiple AD7771 at high speed without using an FPGA (learning curve and time commitment too high). The idea is to use the Teensy 4.1 to implement SPI by...
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