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Thanks I will try adding the 0.1uF capacitors! The existing decoupling 10uF caps are approx. 2.5mm from the pin. PCB traces on the isolated gnd side are 10mils / 0.254mm wide, would that qualify as skinny? In my understanding this should be ok. The PCB is 4 layers. Post-isolator, the stack is...

I didn't think about propagation delay from the isolator, thank you for your input! I will consider this in the next iteration of the design, and try bypassing the isolator for now. Propagation delay however would just affect the timing of my SPI protocol but should not have an effect on the...

Thank you. One output line from the ISO7340 is carrying the isolated "manual" SCLK from the Teensy and going directly to the SCLK input of all four ADCs. I considered it might be a load matter but total capacitance should be around 40pF so shouldn't be a problem?

Thanks! Yes I need to use manual controls so I can read the data from 4 ADCs at the same time. Basically the same "manual" SPI read instruction will feature reading and storing incoming bits from four lines. Would changing the Teensy slew rate help even though there is a digital isolator...

Hi everyone, for a university project I am trying to implement simultaneous readout from multiple AD7771 at high speed without using an FPGA (learning curve and time commitment too high). The idea is to use the Teensy 4.1 to implement SPI by bit banging, request data from the ADCs by shared...