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It is not clear from sgtl5000 datasheet what RATE_MODE actually controls inside the chip (they simply do not disclose it!). Suppose it controls front end interpolating/decimating filter only to produce the 1/2,1/4 or 1/6Fs "effective" sampling rate samples while assuming the same (i.e. Fs) LRCLK...

Hello, I need help with i2s library. It looks to me that the one implemented in Teensy's Audio uses DMA to move audio data in and out. Does anyone has/knows about i2s codes/library for K20 MCU that uses simple read/write operations to the sgtl5000 instead? I need it to simplify my sgtl5000...

Hello everyone, as promised I come back to share my experiences with NXP on that chip. I've tried to squeeze out any useful information from NXP using both their forum as well as direct dialogue with supporting AEs. After about 3 weeks of messaging back and forth I have to declare complete...

Sure, but so far they're not so helpful... Here is the link: https://community.nxp.com/t5/Other-NXP-Products/sgtl5000-datasheet-ambiguity/m-p/2157780/emcs_t/S2h8ZW1haWx8dG9waWNfc3Vic2NyaXB0aW9ufE1FUks1MEwwSjZGRjJVfDIxNTc3ODB8U1VCU0NSSVBUSU9OU3xoSw#M29794

Pete, again many thanks to you and everyone participated in this thread! I will try to get explanations from NXP and report here if they're helpful

Thank you very much, Pete. Miraculously it works on my 3.2 board! But man, honestly, I do not understand, why... I measure mclk clock and it is indeed 2MHz. Their datasheet must be totally screwed up!

Thank you for the link. In your code you address sample rates 32kHz and above. I have no issues with those sample rates. I tried to set Fs=8000Hz and your function returns mclk=2,051,282Hz which is below minimum supported by sgtl5000 (again, according to their datasheet, which - as Paul says -...

Even if you're right about RATE_MODE and SYS_FS, the question still remains: what these setting do in the master mode? BTW it looks like you have implemented Master mode for Teensy4.x, correct? So maybe we can be in a better shape with Teensy4.x? :)

Thank you very much for this code. Unfortunately it may not work for Fs I am interested in. For ex. if we assume F_PLL=96MHz (as in Teensy3.2) your code gives: Fs=8000Hz {8, 375} -> MCLK = 96MHz*8/375 = 2,048,000Hz Fs=11025Hz {73, 2483}->MCLK = 96MHz*73/2483 = 2,822,392Hz As you can see both...

If this is the case I have no comments...

Paul, first of all thanks for your reply. Here are my comments. 1. Let me clarify just in case. I have understood from reading your code that you're using codec in slave mode only. I do not have intention to change that so there is no need to address this issue. 2. I have verified using scope...

Also, excuse me my curiosity but isn't it required to modify sgtl5000 settings as well to support whole bunch of sampling rates that you mention? Thanks!

Thank you very much, but it looks like it can compile only for Teensy4. I need it for Teensy3.2. Is there one? Thanks!

well, I set #define AUDIO_SAMPLE_RATE_EXACT 11029.41176 however the tone it produces is much higher pitch (4x, I guess). (I use Part_1_02_Hardware_Test.ino from Teensy Audio library Examples) What else is needed to make it work? PS I understand what Fs generally means. I ask about what it...

Hello, currently Audio lib supports only 44.1kHz sample rate (hard coded). However sometimes it is advantageous to use other ones as well (for ex. 22.05kHz or 11.025kHz). It looks like the chip has support for that in its CHIP_CLK_CTRL register (SGTL5000 Datasheet Rev. 7, 1/2022, Table 18 p32)...