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  1. R

    T4.0 DMAMEM Acting Different than RAM1 Memory

    This worked, Thank you! (For completeness on this thread here is how I used the functions): void binBuffer() { if(myRXFlag==1) { if(!firstTime) { arm_dcache_delete(dmaBuffer2, sizeof(dmaBuffer2)); delay(1); binDMABUFFER(2); } while(myRXFlag==1){}; } else...
  2. R

    T4.0 DMAMEM Acting Different than RAM1 Memory

    Thank you for the quick response! I think I am following, but maybe you can confirm... So my dma is reading data from spi and directly putting it in memory, however, since there is a cache, when I go to read from that memory it thinks I should be looking at the cache and not the actual memory...
  3. R

    T4.0 DMAMEM Acting Different than RAM1 Memory

    Long story short; I have a teensy 4.0 acting as a spi slave to a 24bit AD7764 ADC. I have set it up so that I use DMA to transfer the spi data into two alternating buffers. In the current scenario, while the DMA is in buffer1, I am accessing/doing stuff with the other buffer2. If the dma is...
  4. R

    ADC Data Recording with SpiSlave and DMA....

    Hello, I am trying to interface a Teensy4.0 and a ADC:AD7764 ADC. The ADC acts a spi master sending out 32bit data samples at 156KS/Sec. I have it hooked up to the SPI interface on the TEENSY and am able to successfully read data at a slow (slower than 156KS/S rate) by manually reading the...
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    SPISlave_T4

    Pin10 is connected to the frame sync output from the ADC. So it is driven low while the ADC is outputting data. It is driven low for 32 bits at 20MHz (1.6uS) then driven high again. I think the issue is that the next time it is driven low again is just about 7uS later. Is 7uS enough time to get...
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    SPISlave_T4

    SPI Slave without interrupts?? Hello, Will this only work using interrupts? My issue seems to be that the RX Interrupt is happening too fast, and hanging up my Teensy. If I disable the interrupt, will the rx bits get written to the FIFO automatically? I am having trouble using the teensy4.0...
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