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Sometimes you've got to fight the compiler, and sometimes it works with you ;)

I think I understand your solution now... You are using all pins in GPIO9 to get 16 bits #define CORE_PIN24_BIT 12 #define CORE_PIN25_BIT 13 #define CORE_PIN19_BIT 16 #define CORE_PIN18_BIT 17 #define CORE_PIN14_BIT 18 #define CORE_PIN15_BIT 19 #define CORE_PIN17_BIT 22 #define...

Your code seems to only be reading 4 pins and some of them are invalid. Also GPIO6 only gives us 10 pins of the pins we need. I have been modeling a solution with the following pins. [ GPIO7 | GPIO9 | GPIO6 | GPIO6 ] [10, 12, 11 | 2, 3, 4 | 19, 18, 14, 15 | 17...

That is wonderful!!! Could you share your full code?

I wrote some rough code and it looks like using the above code for getting the 10 bits from GPIO6 shaves 3ns off of the SHIFT,OR method. That brings us to an avg of 50.0ns per 16bit read. I will try to write some code using XBAR and test if that can outperform what we're doing with multiple...

That's a great point, since the M7 has dual load pipeline along with parallel ALU1 it may be able to do the shifts in parallel.

I checked and the exact timing on the OR combined method is ~50ns reads. So I tried using BFI and for some reason it is 9ns slower than using my OR combined method. data = GPIO7_DR & 0b00000000000000000000000000000111; asm volatile("bfi %0, %1, 3, 3" : "+r"(data) : "r"(GPIO9_DR >> 4))...

Do you think it would be possible to "fake" continuous pins by using an XBAR configuration that copies your desired pins onto an unused/unpopulated) set of GPIO? I think it would be really useful to be able to use FlexIO for this kind of thing. I wonder if using XBAR would make it work. EDIT...

I have come up with a way to do this using the longest IO runs I could find... I used 4 different runs in GPIO6, GPIO7, and GPIO9 and shifted them together. For reference here were my notes. #define CORE_PIN10_PORTREG GPIO7_DR #define CORE_PIN11_PORTREG GPIO7_DR #define CORE_PIN12_PORTREG...