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  1. D

    Level shifting a 5V input down to 3.3V for Teensy 4.0

    I was worried that a voltage divider will induce some long timescales into the system. I suppose it's worth implementing and seeing if the delays it adds are too long for what I need, which needs to have at least 30 ms temporal precision, optimally much more precise than that.
  2. D

    Level shifting a 5V input down to 3.3V for Teensy 4.0

    I have a question about how to properly convert a signal to be compatible with the Teensy 4.0 board. I have an inverted 5V TTL signal coming from this device: https://www.pulseresearchlab.com/collections/rf-switches-scanners-gates/products/prl-601t?variant=40597751234675 The signal relates to...
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