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  1. BertG

    Magnetic Encoder not working with teensy 4.1 but is with teensy 3.2

    Hi, a logic/scope connected to CS, CLK, Data will tell you the truth -always helps (especially in discussion with a SW-engineer who believes in his code 😁). Setup- and Hold-times need to be respected as specified in the timing diagram above. Otherwise try-and-error-sessions experimenting with...
  2. BertG

    LPSPI: every byte transmission followed by unwanted clock repetition

    Hi! After endless hours or testing and digging deep (with no success) we kicked the WIZNET850IO off the board and replaced it with a simple Add-On PCB which sits on spot of the WIZNET module and provides a RJ45 (with magnetics) jack and "short" (*) connection to the Ethernet signal on...
  3. BertG

    LPSPI: every byte transmission followed by unwanted clock repetition

    Hi, we are using Teensy4.1 with a LPSPI connection to a WIZNET805IO (WIZNET5500 chip) module. For some reason every data byte sent (data bits and 8 clock cycles on the logic are ok, timing is perfect) is followed by another 8 clock cycles with MOSI staying at HIGH level which confuses the...
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