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Those times look good. Thanks. If you can start the PXP as early as possible you can do some of it in the vertical blanking period. I haven't had any time recently to look at all this. I hate to say it, but after stumbling around trying to roll something at the time I threw it at chatgtp...

Sorry I didn't realise that. Will need someone more knowledgeable to answer that then.

So im guessing you would need to set the MUX on the pin back to standard io. You will need to know what bank you are using and the pin. IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = The different configurations for the pins are in the datasheet

I've never used LVGL but it always seems to pop up with microcontrollers etc. Do you design your ui on a pc or something rather than hard coding things? Sorry I wasn't very clear. I'm not using the PXP for scaling or rotation. This is done in software on the cpu. It's reading a stored image...

So will this fall within your use case of copying buffers from lvgl? Doing some test image Scaling, Rotation and transparent pixels. All running at 50hz done in software Source image is 128 x 128.

Very nice!!! The 800 x 480 x 2 seems pretty quick. As an aside. You could try and allocate the buffers into different banks of memory (think it's 4 x 4mb each spaced sequentialy) im curious if that makes a difference. I believe there's a little less switching required on the sdram.

How are you doing the copy sdram to sdram? Just a memcopy? I found it faster to burst read an image row (800 x uint16_t) into a local buffer on the stack, then output that in a burst back to sdram.

Yes its a pretty good panel. I had the non IPS version from them before which was not as good (When viewing from the side the colours seemed to change) The only downside is the 2 Ziff cables are far away from each other. I had gone away fromm the pixel pipeline but found an old build with it...

Interesting!!

Whats interesting. Zooming in is actually a lot faster too. As when we are zoomed in there is a lot less of the source image to read from sd ram (We only read the rows required to go to the destination image) So zoomed in at its peak in the video is only 5 milliseconds to read SDRam, scale...

Did some nearest neighbour image scaling using software. (I'm pretty sure the PXP uses nearest neighbour too) I couldnt get Bilinear filtering work, however i think that would be way to slow in software Nearest neighbour is quite quick. Reading and writing non scaled 800 x 480 image from...

I tried some full sized images, 800 x 480 in 24 bit packed format. Not using the pixel pipeline. The fastest i could get was: Image in SDRam, reading from SDram then copying into the Backbuffer on SDRam. 13.9 milliseconds Image saved to onboard Flashmem. Then read to back buffer. 16.2...

I did some tests running the backbuffers and display in rgb565 mode (Sdram clocked at 198mhz again) Backbuffer size is 384000 * uint16_t. All this is done while the LCDIF is outputting to the display at 50hz Pixel Pipeline time clearing the backbuffer with no CPU access. 8.66 milliseconds No...

Sure. Give me a bit though to tidy it up. At the moment im running 3 seperate projects for simplicities sake. 32 bit, 24 bit and 16 bit, as all the primitive drawing routines take in different colour values. Exactly! It took me the third itteration to get this board right. The first 2...

Thats interesting to know. Thanks Yes. Unfortunately at least the LCDIF will be reading the Sdram while anything else is going on with it. I don't remember how much exactly, but setting the backbuffers in different banks (The SDram is divided into 4 even banks) did make a difference on...

I ordered one of dogbones boards and got it stable at 221mhz with a 10pf capacitor. However I think the routing for the sdram for that board was a replica of the imxrt1060 dev board. There routing pattern would be professional. I can get my board running at 198mhz with or without the...

I've tried many different capacitor values, and i cannot get it to run stable at 221mhz. The best i got using a 20pf capacitor, was using Dogbones Sdram test slightly modified was an average failure rate of 3500 words every 478 million word reads So now ive been doing some testing on an 800...

For what its worth. When sending gps locations I like to use int32_t and multiply the double location by 10 million Using 4 bytes this gives 1.1cm precision Storing gps locations in a float gives best case 1.1 meter precision.

It makes me wonder how well an SRAM chip would compare performance wise. Something like 4 Megabyte IS61WV204816BLL-10TLI. The imxrt1060 datasheet does say the memory controller supports external Sram...

Good idea. I'll give that a go!

Thanks. I'll try a bunch of different values and see if I can get an improvement. It's always bits 8 to 15 that error out (when reading the 32 bit words)

Yes I tried a 10pf and a 6pf. But ive put it down to my lack of professional routing skills. And also in trying to keep power filtering capacitors all to one side of the board they would not be optimally placed.

Thanks! Definitely wouldn't have been able to do it without you and rezo

No you would have to route one yourself. I didn't have any use for one and initially was just going to be 3.3v only. I added 3.3v regulator to be able to power of 5v usb.

I've designed a DIY Teensy 4.1 based board with Sdram with the idea of being able to solder it yourself. (It requires a stencil and solder paste as well). I don't have a hot plate, so i have been heating them with hot air from underneath. It uses the BGA 12x12 chip. Like dog bones board it...

If your just reading a 32 bit register I wouldn't bother with adding the pin definitions (it's a pain) Eg, GPIO7 is the B0,B1 register uint32_t value = GPIO7_PSR; (it's fast this way) I'm not sure what GPIO the 32 bit EMC register is

EMC 0 to 31 or GPIO B0-B1 are the only 2 options for a full 32 bit wide bus The AD_B bank you can get a 16 bit sequential bus. 7 of the lower pins are used for the bootloader. The remaining 32 bit bank is a mix of EMC 32+ and the SDIO banks. Some of the SDIO is used for the bootloader You...

Ahh yep, linked lists are horrible when it comes to caching. You would be doing a lot of out of order memory reading and writing on the psram, which would be killing the effeciency.

This doesn't seem right. Is there anything else going on when setting up your objects in extmem. I would do some profiling with using ARM_DWT_CYCCNT and count how many clock cycles it's taking.

Nice work that looks good!!

I'm pretty sure it just pads the lowest bits as 0's for each colour. So in the 565 format if you had 5 bits of red, when converted to 888 the lower 3 bits would be 0 (1111 1000) This is a lot smaller dynamic range then if doing a proper conversion. 5 bits of red should convert to 1111 1111...

Are you running 24bit or 16bit? I like the speed of 16bit. However from what i can understand having 16bit padded input and 24bit data, it will do the conversion and just pad the lower bits of data with 0's. I dont think this gives as good as a colour range as doing a normal RGB565 to RGB888...

It sure did!!!! 10 hours of trouble shooting this and you have just solved it. i needed to set the DockCLK Polarity. I also needed to reverse the polarity on the Vsync and HSync to get it to work LCDIF_VDCTRL0 = LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |...

So using dogbones board im driving a controllerless 800x480 display from buydisplay.com I've made an adaptor pcb with a constant current driver for the backlight as well as a 40 pin ziff connector (had to hand solder, forgot to click the stencil option) So running in dotclock mode (using...

Of course you can. Back in the day graphical adventure games used to run on 8mhz machines, sometimes taking well over 10 clock cycles per instruction. A teensy 4 runs at 600mhz! It can execute 2 instructions per clock cycles I love seeing unconventional uses for a microcontroller. You...

I had no luck getting SDRAM to SDRAM at a decent speed with DMA. The fastest i could get transfers with copying from 1 buffer in SDRAM to another in SDRAM and SDRAM overclocked to 221 was using an Assembly routine. Load registers 3 to 10 sequentially from SDRAM buffer1 , then output them...

Has anyone tested using edma to copy from sdram to sdram to see how much quicker it is than a memcopy? For example copying an image from sdram into a backbuffer in sdram.

My board from dogbones schematic uses the D version. I had to change a lot off parts to ones JLCPCB had in stock, as well as change a lot of the components to standard components to not get stung with extra setup fees. I do wish there was some ground pins along the b0 and b1 rails. If I recall...

That's awesome! Thanks for that, it's definitely some inspiration and help.

Thanks Jmarsh. Theres another 2 weeks of trying to learn FlexIO and DMA. The setup looks complicated. I might just get a bare display from buydisplay and try to drive one of them with lcdif pxlck mode seeing as ive wrapped my head around that side of things. Will need to set up a constant...

I've tried mixing and matching many different register settings and could not get mpu or vsync only mode to work. Have you got any libraries or code for Flexio and Dma?

So im still bashing my head against a wall here. But i think your right. And if we could get the APBDMA mode working it only supports 16 bit. Is 16 the maximum burst length for sdram reads? Im intent on trying to get data out without using FlexIO. My theory is there would be less memory...

Oh man if I new that was there 3 days ago. I'll have a good look at that, thanks. Is it using the lcd module to output? Currently I'm going to use it on a smart(er) display, ssd1963 (has back buffer memory) but eventually a dumb display. Using the lcdif module for output, you can set dma to...

I've got DogBones board up and running with the replacement flash chip. It works great. Been running some 24bit LCD screen tests. I've been bashing my head against the wall trying to output using the LCDIF without much success. In theory it should all be working. I'm trying to use Vysnc...

So while im waiting for the correct flashmem to arrive to run Dogbones Board i've designed a 4 layer board with SDram using the BGA 12x12 chip (Thanks Dogbone for the memory connection schematic). I've managed to get the dimensions at 60mm x 36mm (About the same length as Teensy 4.1 but double...

Yes that will do it. I can't believe I over looked that.

Dog bones boards arrived today. I've soldered the bootloader chip on and on pressing the button I'm getting 3 red blinking lights. According to pjrc store link that means it's not recognising the flash chip. Realised I've used W25Q128JVPQ instead of dogbones recommended W25Q128JVPIM. Is this...

Thanks! Q1 is DMG2305UXQ-7 Q2 is RUE002N02TL So final question. Supplying 3.3v to USB1_VBUS and USB2_VBUS must be enough to get the whole process working? And USB communication/serial still works with 3.3v on Vbus?

G Thanks Paul. Do you know what transistors are used for Q1 and Q2? I'm struggling to work out the sequence from Q1 to Q2 and PMIC From my understanding we need power on USB_VBUS to get 1.1v output on PMIC. I don't see anything like that on there schematic

Hi Paul. On a DIY board to go exclusively powered by 3.3v, would this work? VIN would be 3.3v This would go into USB1_VBUS and USB2_VBUS. Is 3.3v enough to drive these? In place of the 3.3v regulator in the circuit. If i changed that to a NPN MOSFT AO3400A. Vin goes through here. (Gate...