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    Teensy 4.1 UART DMA interfering with delay() functionality

    Thank you for your advice, I have been playing around with my code and have found that the timing bug is caused by the else if statement in the isr: changing the statement from else if(daddr == (uint32_t)dma_rx_buffer + DMA_BUFFER_SIZE - 1) { to else if(daddr == (uint32_t)dma_rx_buffer +...
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    Teensy 4.1 UART DMA interfering with delay() functionality

    Ah what a silly mistake, thank you for catching that. Unfortunately the behavior is still the same, so there must be some thing else going on, but I would have needed to fix this regardless, so thanks again.
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    Teensy 4.1 UART DMA interfering with delay() functionality

    Hello, I am working on building a data acquisition system for 5x FUTEK LSB206 Load cells with UART output using a Teensy 4.1. The load cells use QIA128 controller chips to interface with a host system via UART, which is more thoroughly documented here. The load cells offer a "Stream" Mode...
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