xxxajk
Well-known member
My samples of the IS66WVS16M8FBLL (3.3V version) came in and I put two 16MB chips (32MB total) on a Teensy 4.1. The Startup.c in cores was updated with the new version that is going into Beta 5.
View attachment 37817
Code:32MB default 88MHz test ran for 144.97 seconds. All memory tests passed :-) 32MB CCM_CBCMR=95AE8304 (105.6 MHz) test ran for 123.66 seconds. All memory tests passed :-) 32MB CCM_CBCMR=B5AE8204 (110.8 MHz) test ran for 118.56 seconds. All memory tests passed :-) 32MB CCM_CBCMR=B5AE8104 (120.0 MHz) test ran for 110.65 seconds. All memory tests passed :-) 32MB CCM_CBCMR=55AE8004 (132.0 MHz) - FAILED testing with fixed pattern 0F0F0F0F Error at 710016C0, read 0F0F1F0F but expected 0F0F0F0F
Reran same test and got exact same failure. This failed at a lower speed than xxxajk saw, so I removed 1 PSRAM to see if that was the difference or if it was the fact that I was using 3.3V vs 1.8V parts.
Code:16MB CCM_CBCMR=B5AE8104 (120.0 MHz) test ran for 55.27 seconds. All memory tests passed :-) 16MB CCM_CBCMR=55AE8004 (132.0 MHz) test ran for 51.07 seconds. All memory tests passed :-) 16MB CCM_CBCMR=95AE8104 (144.0 MHz) test ran for 47.09 seconds. All memory tests passed :-) 16MB CCM_CBCMR=75AE8204 (166.2 MHz) testing with fixed pattern 5A698421. Error at 70000000, read DF6B9C23 but expected 5A698421
Now the results matched xxxajk's results so it appears that the issue is likely a bus loading issue. These PSRAM are made of two stacked 8MB parts, so guessing that 2 of them probably load the bus like having 4 of the regular 8MB parts.
To further check this, I added a 2Gb NAND Flash chip and the failure point returned to the same as with the 32MB PSRAM setup
View attachment 37818
Code:16MB + 2Gb Flash CCM_CBCMR=B5AE8104 (120.0 MHz) test ran for 55.27 seconds. All memory tests passed :-) 16MB + 2Gb Flash CCM_CBCMR=55AE8004 (132.0 MHz) testing with fixed pattern 5A698421 Error at 700F7700, read 5A698423 but expected 5A698421
Would have been nice if they worked at the 132MHz that everything else seems to be OK working at, but 120Mhz is still pretty decent.
Perhaps bypass capacitor distance could be a factor too?
C20 is quite a bit away from the second chip, and it failed within the second 16MB.
As a final set of tests, I tried to run my combined PSRAM and NAND Flash test at the default 88MHz bus speed. The PSRAM test passed as expected but received an error starting QSPI Disk which I think was expected since littleFS needs to be updated to work.
I then downloaded @h4yn0nnym0u5e revised LittleFS.cpp file and tried it again. https://github.com/h4yn0nnym0u5e/LittleFS/tree/main/src
It compiled and downloaded but got no output. The PSRAM test didn’t even seem to start. I did not see a revised LittleFS_NAND.cpp file so perhaps that was the issue? Not sure if both files need to be modified for NAND or I was just pulling from the wrong place.