Not sure it is doable...
The LPSPI clock speed is setup from the CCM tree and their is 4 choices for which starting speed as you can
see below:
```
void SPIClass::setClockDivider_noInline(uint32_t clk) {
// Again depreciated, but...
hardware().clock_gate_register |= hardware().clock_gate_mask;
if (clk != _clock) {
static const uint32_t clk_sel[4] = {664615384, // PLL3 PFD1
720000000, // PLL3 PFD0
528000000, // PLL2
396000000}; // PLL2 PFD2
// First save away the new settings..
_clock = clk;
uint32_t cbcmr = CCM_CBCMR;
uint32_t clkhz = clk_sel[(cbcmr >> 4) & 0x03] / (((cbcmr >> 26 ) & 0x07 ) + 1); // LPSPI peripheral clock
```
in ::begin() we default setup that register values.
CCM_CBCMR_LPSPI_PODF(2) | CCM_CBCMR_LPSPI_CLK_SEL(1); // pg 714
So we start off with 720mhz clock. / 3 = 240mhz
The clock divider can be 0-255 (add 2 to it, so: min speed is about .93mhz with default settings.
But: after SPI.begin, you can updat the CCM_CBCMR and maybe choose the last option:
396mhz set PODF(7), so divide by 8. then / 259 and you can go as slow as: .192Mhz