Basic SPI issue (glitches on CS)

F

FLL-Freak

Active member
I am using a Teensy 4.1 to control an SPI slave device on the primary peripheral. Using the basic TeensyDuino architecture. When looking at the signals on a logic analyzer (Logic pro 16) I see lots of glitches on the CS, CLK lines when the MOSI and CLK change states. For whatever reason, the MOSI line appears to be immune. I have worked backwards from my full implementation to now the most basic setup. Just the Teensy connected to my laptop (or power bank) and the output pins direct to the logic analyzer. All the voltage conversion and actual device have been removed. The code was similarly cut down to bare bones and is included here.

In debugging I have tried:
* The SPI1 port with the same effect.
* Bit bang the SPI. I still see glitches on all lines when edged occur on the others.
* It did attempt to play with the drive strength and frequency response fields for those pins, but it is not clear I did this right as I saw little difference.

I must be doing wrong as I can't image that this chip has these intrinsic issues.
I love this board for its blazing speed and vast memory capabilities. I have used it in the past but never with SPI.
Hopefully someone that point out my error.

(edit 1) Could I need more decoupling capacitance then is already on the board?
(edit 2) I tried to run the DigitalPotControl sample with the same results. Glitches on the CS line. I used this same code on a Pro Micro and had no glitches. I am now wondering if I just have a bad board.
(edit 3) I pulled another Teensy 4.1 from another project and it shows the same glitches. So likely the board is OK. :(



Code: 
#include <SPI.h>      

int PIN_CS     = 1;
int PIN_MOSI   = 11;
int PIN_MISO   = 12;
int PIN_CLK    = 13;

SPISettings setting(1000000, MSBFIRST, SPI_MODE0);


//**********************************************************************
//**********************************************************************
void setup()
{

  pinMode(PIN_CS,   OUTPUT);

  digitalWrite(PIN_CS,   HIGH);

  SPI.begin();
 
  Serial.begin (115200);
  Serial.println("Start");          
}


//**********************************************************************
//**********************************************************************
void loop()
{
 
  SPI.beginTransaction(setting);

  digitalWrite(PIN_CS,  LOW);

  SPI.transfer(0x55);

  digitalWrite(PIN_CS,  HIGH);

  SPI.endTransaction();

  delay(1);

}
 
Last edited:
The SPI on Teensy 4.1 works fine as demonstrated by thousands of successful implementations, my own included. It is also unlikely that you have a bad board. Actual bad Teensy boards out of the bag are very rare.

Doing a Google search on "Logic Pro 16 SPI glitch", I see comments that the input structure of the device can cause false glitches to appear in its read-out. Unless you are experiencing actual SPI errors, I would be inclined to dismiss the glitches you are seeing as being related to the logic analyzer itself rather than the Teensy. It looks like they provide a software glitch filter to help filter out these false glitches. https://support.saleae.com/user-guide/using-logic/software-glitch-filter

Here is a link with some more info and suggestions from the Saleae website for dealing with glitches in general. https://support.saleae.com/troubleshooting/seeing-spikes-in-digital-capture

In an actual system, if you are driving the SPI bus for any distance or with several devices on it, it can be beneficial to insert a series resistor into the CLK and MOSI lines near the Teensy to dampen any signal reflections. Something in the 50-75 ohm range generally work fine.
 
For what it is worth, I sometimes see glitches when I view SPI on Logic Analyzer. Somethings I found that help, is to switch the voltage range of the analyzer. (Under Device settings) I set for 3.3+v and that usually helps.

Also trying to make the sampling rate an even multiple of your SPI clock speed helps as well.
 
Thank the both of you (KenHahn and KurtE) for your Christmas Eve answers. They were the gift I needed.
As it turns out the Logic Pro 16 is a new addition to my arsenal and I had failed to realize that the logic level transition voltage was selectable. Setting it for 3V3+ seems to have solved my immediate problem. I will certainly take some time to try to learn more about my Logic Pro. I had the older Logic 8 that did not offer these extra goodies. Those links will make fun reading.
 
Could you please provide a circuit diagram for your setup? Also, a picture.

Pending that, two ways to generate glitches between lines are cross-talk and "ground bounce".

There are others, but those are two of the most popular.

But, let's see a schematic and a picture and see if we can figure it out.
 
DrM said:
Could you please provide a circuit diagram for your setup? Also, a picture.

Pending that, two ways to generate glitches between lines are cross-talk and "ground bounce".

There are others, but those are two of the most popular.

But, let's see a schematic and a picture and see if we can figure it out.
Click to expand...

The schematic is as simple as possible. Just the bare board, a USB cable back to a laptop, and the clip on leads for the logic analyzer. So no extra circuitry. As it turns out, it was an instrumentation error. The logic analyzer has selectable voltage ranges for different logic families. I had it improperly selected for 1.8 volt logic not 3.3.
 
Yes, I just read the fine print in the OP. That sounds right.

For me, the instrument of choice for something like this, is an oscilloscope.
 
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