BCLK Generation (I2S)

[JurMa1]

Hello at everyone ,

I'm making an audio applikation (Teensy 3.5) with an I2S MEMS Mikrophone. I've connected everything and it is working fine, but I'm curious how the BCLK (Bit Clock) is generated.

By reasearch i found out that the BCLK is generated by the MCLK (which is generated by a division and a fraction of a PLL). When I go into this line

I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1)| I2S_RCR2_BCD | I2S_RCR2_DIV(1);

I see, that there is a BCLK for the receiver and the transmitter. I also see that there is a divisior for the BCLK.

Let's say i want a samplerate of 8 kHz with 16 bit integer (you'll see later why i choosed this). That would make the MCLK at a frequency of 2 048 000 Hz (MULT is 32, DIV is 1875, so (120 000 * MULT / DIV / 256 / 32 kHz). If you go to the Manual of the Chip you'll see (Page 1740) that the DIV of the BCLK will divide down the audio master clock to generate the bit clock when configured for an internal bit clock with a division value of (DIV + 1) * 2. The BCLK therefore would be 512 kHz (around 0.5 MHz).

If you go to the Wikipedia lage of I2S and you go to the second Reference (http://www.analog.com/media/en/technical-documentation/technical-articles/MS-2275.pdf) you can extract the information "An I2S data stream can carry one or two channels of data with a typical bit clock rate between 512 kHz, for an 8 kHz sampling rate [...]" (page 2, last paragraph at the left side). Informations like this are also in some manuals for microphones so I assume that this is the correct one (Example: https://www.digikey.com/product-detail/en/knowles/SPH0645LM4H-B/423-1405-2-ND/5332440 Datasheet page 07, Interface description).

But on the Wikipedia page (https://en.wikipedia.org/wiki/I²S) there is a diffrent formula for the BCLK.

BCLK = samplerate * bits per channel * number of channels

Therefore the samplerate would be 8 kHz * 16 * 2 = 256 kHz (0.256 MHz).

Which of these informations are correct?

 

[WMXZ]

BCLK = samplerate * bits per channel * number of channels

this is the correct formula

You determine the multiplier and dividers accordingly.
It may, however, not be possible, to find practicable values to derive bit clock from PLL or system clock.
This is valid for I2S MEME microphones

For other I2S devices (e.g. SGT5000 in Audio card) you need a MCLK line that is a high multiple of the frame clock (typically 64,128,256)
which further constrains your capability to generate the desired sampling frequency.

 

[JurMa1]

okay. Then what does this command do?

I2S_RCR2_DIV(1)

And why is my BCLK frequency right for the frequencies in the manuals? Am I mistaking something?

 

[WMXZ]

okay. Then what does this command do?

I2S_RCR2_DIV(1)

And why is my BCLK frequency right for the frequencies in the manuals? Am I mistaking something?

without complete code, cannot say anything
my own code has no value 1 in I2S_RCR2_DIV(1), but is estimated from F_CPU or system clock.

Edit:
I usually follow this:
/ rules to generate click dividers
// MCGPLLCLK=F_CPU // is set by _MICS(3)
// MCLK = MCGPLLCLK*(iscl1+1)/(iscl2+1)
// BCLK = MCLK/2/(iscl3+1)
// LRCLK = BCLK/(2*nbits); // division by is to have 32 bits within frame sync (BCLK) need 64 bit for I2S-MEMS
//

 

[PaulStoffregen]

Am I mistaking something?

Yes, you are. You're not alone. I also made this "mistake" until recently, and it worked perfectly well with the SGTL5000 and many other chips.

But it turns out some I2S chips, particularly MEMS mics, require a BCLK to LRCLK ratio of 64, even though they don't actually make any use of those extra 16 bits. The audio lib code was changed not long ago to use this ratio and simply ignore half of the incoming bits. This seems to be the format which is actually compatible in practice with all I2S chips. If you use a BCLK to LRCLK ratio of 32, as I originally did in the early days of the audio lib, it works with many chips but some just will not work. You can find many old threads on this forum where those incompatible chips were discussed. Thankfully, those days are behind us now. I recommend you keep the BCLK to LRCLK ratio at 64, even it seems unnecessary.

 

[PaulStoffregen]

You might also take another look at the specs on that mic you mentioned. The datasheet seems to say in the table on page 2 and the text on page 7 that the minimum clock frequency is 2.048 MHz. The fixed BCLK to LRCLK ratio is also mentioned on page 7. It won't work at all, at any clock speed, if you go with the ratio of only 32.

So with this mic, you must get the ratio right, but even that will probably not allow the chip to work the way you're planning. The specs table and description on page 6 say the mic goes into a low power sleep mode if BCLK drops below 900 kHz. This part simply does not seem to support the low sample rates you want.

Of course, you can read the data at a higher sample rate, run the data through a low-pass filter to remove the unwanted high frequencies, and then just discard the samples you don't want. All of these are pretty simple to do with the audio library. Use the queue object to get the actual raw data after the low pass filter. Just make sure you don't neglect the low pass filter step, so you don't end up with terrible Nyquist aliasing.