Something funky with this Serial5?
Serial5.begin(6000000); // p# 20 Tx & 21 Rx
With 5 UARTS 1<>2 were initially paired and working crossed to each other
Then added the other three chained 4>>5>>6>4 :: Arrays made the code smaller
> 5 kept getting errors when others would not.
> moved #4 to feed itself, 5 still an issue with 6 { #4 alone fine }
> moved 5 to feed itself and still an issue { 4<>6 fine }
> dropped #5 from the list and the other 4 no errors in two pairs 1<>2 and 4<>6
> same results SDRAM sdram_malloc, or with DMAMEM malloc
> have a
delayMicroseconds(15); in the readBytes() loop: extended to 185 us and no help for #5
> used diff jumper wires and header solder looks good.
> sdram_malloc()'s are done in an array 3 per UART - moving #5 from the list moved it from #4 to #5 in the list so it isn't a problem with memory location (and same with DMAMEM).
>> Start of message 100% - but not getting full length into buffer in time?
>
@KurtE Assuming all the UARTS using the same class code and nothing odd about Serial5?
CODE HERE:
https://github.com/Defragster/EVKB_1060/tree/main/mallocSDRAM/examples/UART_extmem_ARR
Output snip: Even with 4 active 6M ports the limit is probably a few million too many UART interrupts
Serial2 Here 128812 #B:20074 #ERR:0 /s=22 B/s=1766512 MEM=sdram_malloc
!"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz
!"#$%&'()*+,-./0123456789:;<=>?@ABCD
Serial1 Here 128809 #B:20074 #ERR:0 /s=22 B/s=1766512 MEM=sdram_malloc
!"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz
!"#$%&'()*+,-./0123456789:;<=>?@ABCD
Serial6 Here 128821 #B:20074 #ERR:0 /s=22 B/s=1766512 MEM=sdram_malloc
!"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz
!"#$%&'()*+,-./0123456789:;<=>?@ABCD
Serial4 Here 128816 #B:20074 #ERR:0 /s=22 B/s=1766512 MEM=sdram_malloc
!"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz
!"#$%&'()*+,-./0123456789:;<=>?@ABCD
> 1,766,512 B/sec with 4 ports Rx'ing and Tx'ing those bytes? So, only 1.7M up from 1.1M
> hardly enough speed to challenge SDRAM
> but the 14-17 sdram_malloc()'s are perfectly functional!
@mjs513 if repro desired with sketch above '#define USED_UARTS 4' excludes #5 unless edited from 4 to 5
Wiring: 1>16, 0>17 and 24>B1_01, 25>B1_00 and #5: 20>21
> should try here on a T_4,1 with DMAMEM