The SDRAM part is spec'd at 166MHz. Not sure why clockdiv = 5; set for 133 MHz ? It should be running at 166 MHz based on part spec and the testing done here.
AFAIK the cap was only included on these DEV boards because the NXP board may have had it. The value is wholly wrong for any use - and without the cap the SDRAM runs seemingly fine at 198 MHz - and with 'HACKY' CAP adjustment it works somewhat at 212 - but that was just answering a question Paul had and with a proper cap it may function at 212 MHz ... but way OC'd for marginal gain over 198 MHz.
@jmarsh - the silkscreen notes 'DevBoard' and the prior rev didn't seem to work at all for
@Dogbone06 - he only made two with the first coming here to quickly see it work over Christmas weekend - so another batch of 5 without changes was made for this wider release.
The extmem won't have support - that requires larger changes in PJRC/cores. So the SDRAM_t4 library was extended to offer dynamic malloc support - but nothing compile time static like for PSRAM on the T_4.1 PJRC product at this point with TD 1.59 in late beta with minimal MPU change to allow the SDRAM_t4 lib to work without edits to the main startup.c file - and include the needed SEMC raft of #defines for addressing access {in beta 5 AFAIK - until then manual overwrite}.
Also complete pin support is lacking from T_MM - even though it is identified as a T_MM because it has a 16 MB Flash on the bottomside. The left side labels follow from T_MM but the right side - while having some T_MM pins - was designed as 16 bit port support for the work
@Rezo has with larger displays.
Yes, it might be nice to control the SDRAM speed from a parameter - and the NOCAP option is just a DevBoard artifact as it has been found that it is not required or desirable with the code Paul supplied when the errant CAP is removed.
Not claiming to be qualified to use a soldering iron - but it worked easily and far enough from the MCU chip that flux paste residue wiped off without needing to wash the board. Even managed to solder and remove 30ga WW wires for CAP testing without issue. So, suggest removing it given the tools and some experience fo knowing which end it the hot one
The change to 166 MHz with clockdiv = 4; was just pushed to github. The CAP did not live long on the board here and most extensive testing done at 166 MHz or higher so use at 133 MHz was early or by accident.
I need to get back to cleaning the examples I touched - With busy holidays been on a break with wife having a couple days off - and it being awful cold with the woodstove getting more attention.