/*
* Copyright 2017-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_debug_console.h"
#include "fsl_device_registers.h"
#include "pin_mux.h"
#include "clock_config.h"
#include "board.h"
#include "fsl_semc.h"
// #include "stdio.h"
#include "system_MIMXRT1062.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define EXAMPLE_SEMC SEMC
#define EXAMPLE_SEMC_START_ADDRESS (0x80000000U)
#define EXAMPLE_SEMC_CLK_FREQ CLOCK_GetFreq(kCLOCK_SemcClk)
#define SEMC_EXAMPLE_DATALEN 12*1024 // (0x1000U)
// #define SEMC_EXAMPLE_WRITETIMES (1000U)
#define EXAMPLE_LED_GPIO BOARD_USER_LED_GPIO
#define EXAMPLE_LED_GPIO_PIN BOARD_USER_LED_GPIO_PIN
/*
GPIO_PinWrite(EXAMPLE_LED_GPIO, EXAMPLE_LED_GPIO_PIN, 1U);
*/
/*******************************************************************************
* Prototypes
******************************************************************************/
extern status_t BOARD_InitSEMC(void);
static void SEMC_SDRAMReadWrite32BitAll(void);
static void SEMC_SDRAMReadWrite32Bit(void);
static void SEMC_SDRAMReadWrite16Bit(void);
static void SEMC_SDRAMReadWrite8Bit(void);
/*******************************************************************************
* Variables
******************************************************************************/
uint32_t sdram_writeBuffer[SEMC_EXAMPLE_DATALEN];
uint32_t sdram_readBuffer[SEMC_EXAMPLE_DATALEN];
/*******************************************************************************
* Code
******************************************************************************/
status_t BOARD_InitSEMC(void)
{
semc_config_t config;
semc_sdram_config_t sdramconfig;
uint32_t clockFrq = EXAMPLE_SEMC_CLK_FREQ;
/* Initializes the MAC configure structure to zero. */
memset(&config, 0, sizeof(semc_config_t));
memset(&sdramconfig, 0, sizeof(semc_sdram_config_t));
/* Initialize SEMC. */
SEMC_GetDefaultConfig(&config);
config.dqsMode = kSEMC_Loopbackdqspad; /* For more accurate timing. */
SEMC_Init(SEMC, &config);
/* Configure SDRAM. */
sdramconfig.csxPinMux = kSEMC_MUXCSX0;
sdramconfig.address = 0x80000000;
sdramconfig.memsize_kbytes = 32 * 1024; /* 32MB = 32*1024*1KBytes*/
sdramconfig.portSize = kSEMC_PortSize16Bit;
sdramconfig.burstLen = kSEMC_Sdram_BurstLen8;
sdramconfig.columnAddrBitNum = kSEMC_SdramColunm_9bit;
sdramconfig.casLatency = kSEMC_LatencyThree;
sdramconfig.tPrecharge2Act_Ns = 18; /* Trp 18ns */
sdramconfig.tAct2ReadWrite_Ns = 18; /* Trcd 18ns */
sdramconfig.tRefreshRecovery_Ns = 67; /* Use the maximum of the (Trfc , Txsr). */
sdramconfig.tWriteRecovery_Ns = 12; /* 12ns */
sdramconfig.tCkeOff_Ns =
42; /* The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.*/
sdramconfig.tAct2Prechage_Ns = 42; /* Tras 42ns */
sdramconfig.tSelfRefRecovery_Ns = 67;
sdramconfig.tRefresh2Refresh_Ns = 60;
sdramconfig.tAct2Act_Ns = 60;
sdramconfig.tPrescalePeriod_Ns = 160 * (1000000000 / clockFrq);
sdramconfig.refreshPeriod_nsPerRow = 64 * 1000000 / 8192; /* 64ms/8192 */
sdramconfig.refreshUrgThreshold = sdramconfig.refreshPeriod_nsPerRow;
sdramconfig.refreshBurstLen = 1;
return SEMC_ConfigureSDRAM(SEMC, kSEMC_SDRAM_CS0, &sdramconfig, clockFrq);
}
#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
#include "fsl_cache.h"
#endif
#define ARM_DWT_CYCCNT (*(volatile uint32_t *)0xE0001004) // Cycle count register
uint32_t microsSim() {
// return MSDK_GetCpuCycleCount()/600;
return ARM_DWT_CYCCNT/600;
}
#define micros microsSim
/*!
* @brief Main function
*/
int main(void)
{
/* Hardware initialize. */
BOARD_ConfigMPU();
BOARD_InitBootPins();
BOARD_InitBootClocks();
CLOCK_InitSysPfd(kCLOCK_Pfd2, 29);
/* Set semc clock to 163.86 MHz */
CLOCK_SetMux(kCLOCK_SemcMux, 1);
CLOCK_SetDiv(kCLOCK_SemcDiv, 1);
USER_LED_INIT(1U);
BOARD_InitDebugConsole();
PRINTF("\n SEMC SDRAM Example Start! 12/21 \n");
PRINTF(__FILE__);
PRINTF("\n float? %f\n", 0.01234f);
PRINTF("\t HELLO WORLD!\n");
if (BOARD_InitSEMC() != kStatus_Success)
{
PRINTF("\r\n SEMC SDRAM Init Failed\n");
}
else
{
PRINTF("\r\n SEMC SDRAM Init Succeeded!\n");
USER_LED_TOGGLE();
}
uint32_t aTime;
/* 32Bit data read and write. */
//aTime = MSDK_GetCpuCycleCount();
aTime = micros();
SEMC_SDRAMReadWrite32BitAll();
aTime = micros()-aTime;
PRINTF("\t ALL Write-Test took %d micros\n", aTime);
USER_LED_TOGGLE();
/* 32Bit data read and write. */
aTime = micros();
SEMC_SDRAMReadWrite32Bit();
aTime = micros()-aTime;
PRINTF("\t Write-Test took %d micros\n\n", aTime);
USER_LED_TOGGLE();
/* 16Bit data read and write. */
aTime = micros();
SEMC_SDRAMReadWrite16Bit();
aTime = micros()-aTime;
PRINTF("\t Write-Test took %d micros\n\n", aTime);
USER_LED_TOGGLE();
/* 8Bit data read and write. */
aTime = micros();
SEMC_SDRAMReadWrite8Bit();
aTime = micros()-aTime;
PRINTF("\t Write-Test took %d micros\n\n", aTime);
PRINTF(" SEMC SDRAM Example End.\n");
GPIO_PinWrite(EXAMPLE_LED_GPIO, EXAMPLE_LED_GPIO_PIN, 1U);
while (1)
{
}
}
void SEMC_SDRAMReadWrite32BitAll(void) {
uint32_t index;
uint32_t datalen = 32 * 1024 * 1024 / sizeof(uint32_t);
uint32_t *sdram = (uint32_t*) EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */
bool result = true;
PRINTF("\n SEMC SDRAM Memory 32 bit Write Start, Start Address 0x%x, Data Length %d !\n",
sdram, datalen * sizeof(uint32_t));
/* Prepare data and write to SDRAM. */
uint32_t aTime;
/* 32Bit data read and write. */
aTime = micros();
for (index = 0; index < datalen; index++) {
sdram[index] = index;
}
aTime = micros() - aTime;
PRINTF("\t ALL Write took %d micros\n", aTime);
PRINTF("SEMC SDRAM Read 32 bit Data Start, Start Address 0x%x, Data Length %d !\n",
sdram, datalen * sizeof(uint32_t));
#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
x // no cache here
DCACHE_InvalidateByRange(EXAMPLE_SEMC_START_ADDRESS, 4U * SEMC_EXAMPLE_DATALEN);
#endif
aTime = micros();
/* Read data from the SDRAM. */
for (index = 0; index < datalen; index++) {
if (sdram[index] != index) {
result = false;
break;
}
}
aTime = micros()-aTime;
PRINTF("\t ALL Read&Test took %d micros\n", aTime);
if (!result) {
PRINTF("ALL SEMC SDRAM 32 bit Data Write and Read Compare Failed!\n\n");
} else {
PRINTF("ALL SEMC SDRAM 32 bit Data Write and Read Compare Succeed!\n");
}
}
void SEMC_SDRAMReadWrite32Bit(void)
{
uint32_t index;
uint32_t datalen = SEMC_EXAMPLE_DATALEN;
uint32_t *sdram = (uint32_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */
bool result = true;
PRINTF("\n SEMC SDRAM Memory 32 bit Write Start, Start Address 0x%x, Data Length %d !\n", sdram, datalen);
/* Prepare data and write to SDRAM. */
for (index = 0; index < datalen; index++)
{
sdram_writeBuffer[index] = index;
sdram[index] = sdram_writeBuffer[index];
}
PRINTF("\n SEMC SDRAM Read 32 bit Data Start, Start Address 0x%x, Data Length %d !\n", sdram, datalen);
#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
DCACHE_InvalidateByRange(EXAMPLE_SEMC_START_ADDRESS, 4U * SEMC_EXAMPLE_DATALEN);
#endif
/* Read data from the SDRAM. */
for (index = 0; index < datalen; index++)
{
sdram_readBuffer[index] = sdram[index];
}
PRINTF("\n SEMC SDRAM 32 bit Data Write and Read Compare Start!\n");
/* Compare the two buffers. */
while (datalen--)
{
if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen])
{
result = false;
break;
}
}
if (!result)
{
PRINTF("\n SEMC SDRAM 32 bit Data Write and Read Compare Failed!\n");
}
else
{
PRINTF("\n SEMC SDRAM 32 bit Data Write and Read Compare Succeed!\n");
}
}
static void SEMC_SDRAMReadWrite16Bit(void)
{
uint32_t index;
uint32_t datalen = SEMC_EXAMPLE_DATALEN;
uint16_t *sdram = (uint16_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */
bool result = true;
PRINTF("\n SEMC SDRAM Memory 16 bit Write Start, Start Address 0x%x, Data Length %d !\n", sdram, datalen);
memset(sdram_writeBuffer, 0, sizeof(sdram_writeBuffer));
memset(sdram_readBuffer, 0, sizeof(sdram_readBuffer));
/* Prepare data and write to SDRAM. */
for (index = 0; index < datalen; index++)
{
sdram_writeBuffer[index] = index % 0xFFFF;
sdram[index] = sdram_writeBuffer[index];
}
PRINTF("\n SEMC SDRAM Read 16 bit Data Start, Start Address 0x%x, Data Length %d !\n", sdram, datalen);
#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
DCACHE_InvalidateByRange(EXAMPLE_SEMC_START_ADDRESS, 4U * SEMC_EXAMPLE_DATALEN);
#endif
/* Read data from the SDRAM. */
for (index = 0; index < datalen; index++)
{
sdram_readBuffer[index] = sdram[index];
}
PRINTF("\n SEMC SDRAM 16 bit Data Write and Read Compare Start!\n");
/* Compare the two buffers. */
while (datalen--)
{
if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen])
{
result = false;
break;
}
}
if (!result)
{
PRINTF("\n SEMC SDRAM 16 bit Data Write and Read Compare Failed!\n");
}
else
{
PRINTF("\n SEMC SDRAM 16 bit Data Write and Read Compare Succeed!\n");
}
}
static void SEMC_SDRAMReadWrite8Bit(void)
{
uint32_t index;
uint32_t datalen = SEMC_EXAMPLE_DATALEN;
uint8_t *sdram = (uint8_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */
bool result = true;
PRINTF("\n SEMC SDRAM Memory 8 bit Write Start, Start Address 0x%x, Data Length %d !\n", sdram, datalen);
memset(sdram_writeBuffer, 0, sizeof(sdram_writeBuffer));
memset(sdram_readBuffer, 0, sizeof(sdram_readBuffer));
/* Prepare data and write to SDRAM. */
for (index = 0; index < datalen; index++)
{
sdram_writeBuffer[index] = index % 0x100;
sdram[index] = sdram_writeBuffer[index];
}
PRINTF("\n SEMC SDRAM Read 8 bit Data Start, Start Address 0x%x, Data Length %d !\n", sdram, datalen);
#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
DCACHE_InvalidateByRange(EXAMPLE_SEMC_START_ADDRESS, 4U * SEMC_EXAMPLE_DATALEN);
#endif
/* Read data from the SDRAM. */
for (index = 0; index < datalen; index++)
{
sdram_readBuffer[index] = sdram[index];
}
PRINTF("\n SEMC SDRAM 8 bit Data Write and Read Compare Start!\n");
/* Compare the two buffers. */
while (datalen--)
{
if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen])
{
result = false;
break;
}
}
if (!result)
{
PRINTF("\n SEMC SDRAM 8 bit Data Write and Read Compare Failed!\n");
}
else
{
PRINTF("\n SEMC SDRAM 8 bit Data Write and Read Compare Succeed!\n");
}
}
/*
// GPT 1MHz micro() manitou
#include <stdio.h>
#include <math.h>
#include "fsl_debug_console.h"
#include "board.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
#include "clock_config.h"
#include "fsl_clock.h"
// micros for SDK using GPT add gpt component to project
#include "fsl_gpt.h"
#define GPTx GPT1
void micros_init() {
// run GPT at 1mhz
gpt_config_t gptConfig;
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
CLOCK_SetDiv(kCLOCK_PerclkDiv, 0);
GPT_GetDefaultConfig(&gptConfig);
// * Initialize GPT module
GPT_Init(GPTx, &gptConfig);
// * Divide GPT clock source frequency by 150 inside GPT module
GPT_SetClockDivider(GPTx, CLOCK_GetFreq(kCLOCK_IpgClk) / 1000000);
GPT_StartTimer(GPTx);
}
uint32_t micros() {
return GPT_GetCurrentTimerCount(GPTx);
}
void delay(uint32_t ms) {
uint32_t t = micros();
while(micros() < t + 1000*ms);
}
#define PRREG(z) printf(#z" 0x%x\n",z)
#define ARM_DEMCR (*(volatile uint32_t *)0xE000EDFC) // Debug Exception and Monitor Control
#define ARM_DEMCR_TRCENA (1 << 24) // Enable debugging & monitoring blocks
#define ARM_DWT_CTRL (*(volatile uint32_t *)0xE0001000) // DWT control register
#define ARM_DWT_CTRL_CYCCNTENA (1 << 0) // Enable cycle count
#define ARM_DWT_CYCCNT (*(volatile uint32_t *)0xE0001004) // Cycle count register
int main(void) {
// * Board pin, clock, debug console init *
BOARD_ConfigMPU();
BOARD_InitPins();
BOARD_BootClockRUN();
BOARD_InitDebugConsole();
micros_init();
uint32_t us = micros();
delay(10);
PRINTF("%d us %d\n",us, micros());
printf("printf %.2f\n",-1.234);
PRINTF("PRINTF %.2f\n",-1.234);
while(1){
delay(1000);
}
}
*/
