Call to arms | Teensy + SDRAM = true

PaulStoffregen said:
I'm made a commit to add finer control over the frequency.

github.com

All finer control over frequency · mjs513/SDRAM_t4@7147e68

Contribute to mjs513/SDRAM_t4 development by creating an account on GitHub.
github.com github.com

This adds frequencies 173,180,187,196,206,216,227,240,254,270,288,etc

Hopefully I didn't break the library? Don't have hardware here to test.
Click to expand...
Legend! Now I can see how fast she'll run :cool:
Can you list all frequencies? What if 288 is still to slow.

Please put the comments here: https://github.com/mjs513/SDRAM_t4/...3c2/examples/CapReadSDRAM/CapReadSDRAM.ino#L4
 
Code: 
CCM_ANALOG_PFD_480_SET = (0x80 | frac) << 8;
Doesn't setting the top bit (0x80) disable the PFD?
 
PaulStoffregen said:
This adds frequencies 173,180,187,196,206,216,227,240,254,270,288,etc

Hopefully I didn't break the library? Don't have hardware here to test.
Click to expand...
Ok was just trying @defragsters memory test and something is way off. Tried running at 198mhz (yes dqs = true) and the 57 test patterns test is taking forever - been sitting here about 5 minutes waiting for it to finish - its still running so stopping it.

EDIT: tried 166Mhz same issue
 
Last edited:
mjs513 said:
Ok was just trying @defragsters memory test and something is way off. Tried running at 198mhz (yes dqs = true) and the 57 test patterns test is taking forever - been sitting here about 5 minutes waiting for it to finish - its still running so stopping it.
Click to expand...
What capacitor do you have on the board?
 
Dogbone06 said:
But the point with DQS is to have a cap, right?
Click to expand...
Yes and no - @jmarsh pointed out to me that at 166Mhz and above still need set useDQS to true, probably because there is still some internal capacitance on the pin.

jmarsh said:
Without a capacitor yes, but the control register must have DQSMD set in those cases. If it's not set there is no chance of those speeds working no matter if the pin is floating or connected to anything.
Click to expand...
Click to expand...

so begining to wonder if we even need it at all
 
PaulStoffregen said:
I'm made a commit to add finer control over the frequency.

github.com

All finer control over frequency · mjs513/SDRAM_t4@7147e68

Contribute to mjs513/SDRAM_t4 development by creating an account on GitHub.
github.com github.com

This adds frequencies 173,180,187,196,206,216,227,240,254,270,288,etc

Hopefully I didn't break the library? Don't have hardware here to test.
Click to expand...
I have tested 227,240,288
They make the board hang and I need to use the boot button to flash again. So not working.
But 221 still works oddly.
 
Try changing this code to this:
Code: 
        CCM_ANALOG_PFD_480_SET = 0x80 << 8;
        CCM_ANALOG_PFD_480_CLR = 0x7F << 8;
        unsigned int frac = roundf(8640.0f / (float)(clock * clockdiv));
        if (frac < 12 || frac > 35) return false; // should never happen...
        CCM_ANALOG_PFD_480_TOG = (0x80 | frac) << 8;
 
jmarsh said:
Try changing this code to this:
Code: 
        CCM_ANALOG_PFD_480_SET = 0x80 << 8;
        CCM_ANALOG_PFD_480_CLR = 0x7F << 8;
        unsigned int frac = roundf(8640.0f / (float)(clock * clockdiv));
        if (frac < 12 || frac > 35) return false; // should never happen...
        CCM_ANALOG_PFD_480_TOG = (0x80 | frac) << 8;
Click to expand...
Works! 288MHz test running!
 
jmarsh said:
Try changing this code to this:
Code: 
CCM_ANALOG_PFD_480_SET = 0x80 << 8;
CCM_ANALOG_PFD_480_CLR = 0x7F << 8;
unsigned int frac = roundf(8640.0f / (float)(clock * clockdiv));
if (frac < 12 || frac > 35) return false; // should never happen...
CCM_ANALOG_PFD_480_TOG = (0x80 | frac) << 8;
Click to expand...
Confirmed tested (no cap) works at 198 and 206mhz
 
Just starting new tests. 1.5pF is on the board so I'm testing it.
Altho it fails.

Code: 
XTMEM Memory Test, 32 Mbyte   SDRAM speed 227 Mhz F_CPU_ACTUAL 600 Mhz begin@ 80000000  end@ 82000000


  --- START 57 test patterns ------ with 3 reReads ... wait ...
#############F....FF...F.....F.........F...F....F..FF....
Test result: 26 read errors


Extra info: ran for 83.26 seconds
 
jmarsh said:
Doesn't setting the top bit (0x80) disable the PFD?
Click to expand...

Yes, you're right. I got that part wrong.


Dogbone06 said:
But the point with DQS is to have a cap, right?
Click to expand...

The pin itself has some capacitance. We don't really know how much, but 5 pF is typical for this type of chip. So when you add a 1 pF capacitor, you're actually testing (probably) 6 pF.

Edit: the PCB trace and pads also add some capacitance. How much depends mostly on the thickness of the FR4 fiberglass between the trace and ground plane underneath. But for a short trace and small SMT pads, it's probably adds less than 1 pF.
 
Last edited:
@PaulStoffregen can you write a complete list of speeds? That will give me all I need to do a real actual speed test of each cap. It will take time, but I'll do it.

Tested the 1.5pF with 227MHz, it fails. But it works with 221MHz so I'd say that's the limit of 1.5pF.
 
Dogbone06 said:
can you write a complete list of speeds?
Click to expand...

How about a program you can run to see them all?

Code: 
#include <SDRAM_t4.h>

SDRAM_t4 sdram;

void setup() {
  while (!Serial) ;
  for (int i=95; i < 370; i++) {
    bool ok = sdram.begin(32, i, true);
    Serial.printf(" clock=%d, %s\n\n", i, (ok ? "Ok" : "Fail"));
  }
}

void loop() {
}

Of course also make sure the line inside SDRAM begin() which prints the actual frequency is uncommented.
 
PaulStoffregen said:
How about a program you can run to see them all?

Code: 
#include <SDRAM_t4.h>

SDRAM_t4 sdram;

void setup() {
  while (!Serial) ;
  for (int i=95; i < 370; i++) {
    bool ok = sdram.begin(32, i, true);
    Serial.printf(" clock=%d, %s\n\n", i, (ok ? "Ok" : "Fail"));
  }
}

void loop() {
}

Of course also make sure the line inside SDRAM begin() which prints the actual frequency is uncommented.
Click to expand...
Oh so what you did to get so much fine tuning is to somehow automate or calculate different clocks. That’s cool!

Program to show all of them is even better than a list. Now I have all I need, this should take a few days but I’ll give some updates during the tests.
 
Just to explain the rationale again, you're trying to find a frequency where it's occasionally failing. Only 26 errors from millions of reads really isn't very much. You might need to go slightly higher.

The idea is to test various (or all) capacitors at the SAME frequency where a substantial number of errors happen. The goal is determine which capacitor is the best choice. At a very high overclock where all tests have some errors, the capacitor which gives the fewest errors would be the best to choose for your future PCB assembly.

If you repeat the test at a slightly lower or higher frequency, you'll probably see a similar pattern. In fact, doing so would (if the pattern is similar) confirm which capacitor gives the best timing margin even at the frequency changes, allowing a very aggressive overclock to almost work, or a less extreme overclock to have no errors. But again, the test is meant to compare capacitors at the same frequency. So I don't recommend making things more complicated by testing with other frequencies until you have a clear picture at one frequency.

Hopefully it's not a huge leap of faith to conclude the capacitor which gives fewest errors with extreme overclocking probably gives the largest extra timing safety margin at rated speed.
 
As you do these capacitor test, try not to think of testing as pass vs fail. Your goal is to run so fast that all tests "fail". You're comparing how much they fail. A capacitor which gives fewer read errors is a better choice than one which gives more read errors. The idea is to learn which capacitor gives the best timing margin, allowing a too-fast overclock to have the fewest errors.

You don't want pass results. If any of the tests "pass" you're probably not running fast enough. Two "pass" results gives you no extra info about which which capacitor was better. You need the tests to "fail" so you can compare which capacitor is better than the other.
 
Using the current latest asking for 'speed = 206' with no cap:
Code: 
Clock set 205.71 MHz

    SUCCESS sdram.init()

    SEND USB to repeat test after completion
    Send '1' for 100 or 'k' gives 1K read repeats and 's' returns to start short test value.
    Progress:: '#'=fixed pattern, '.'=PsuedoRand patterns, and 'F' shows Failed test pattern
    If built with DUAL Serial second SerMon will show details.

Compile Time:: C:\Users\TimLabs\Documents\GitHub\SDRAM_t4\examples\CapReadSDRAM\CapReadSDRAM.ino Jan 28 2024 11:07:03
EXTMEM Memory Test, 32 Mbyte   SDRAM speed 206 Mhz F_CPU_ACTUAL 600 Mhz begin@ 80000000  end@ 82000000

  --- START 57 test patterns ------ with 3 reReads ... wait ...
#############............................................
Test result: 0 read errors

Extra info: ran for 86.35 seconds

  --- START 57 test patterns ------ with 100 reReads ... wait ...
#############............................................
Test result: 0 read errors

Extra info: ran for 2500.23 seconds
Bumping from working 206 to 216 goes to Fails with no cap.
 
Last edited:
defragster said:
Using the current latest asking for 'speed = 206' with no cap:
Code: 
Clock set 205.71 MHz

    SUCCESS sdram.init()

    SEND USB to repeat test after completion
    Send '1' for 100 or 'k' gives 1K read repeats and 's' returns to start short test value.
    Progress:: '#'=fixed pattern, '.'=PsuedoRand patterns, and 'F' shows Failed test pattern
    If built with DUAL Serial second SerMon will show details.

Compile Time:: C:\Users\TimLabs\Documents\GitHub\SDRAM_t4\examples\CapReadSDRAM\CapReadSDRAM.ino Jan 28 2024 11:07:03
EXTMEM Memory Test, 32 Mbyte   SDRAM speed 206 Mhz F_CPU_ACTUAL 600 Mhz begin@ 80000000  end@ 82000000

  --- START 57 test patterns ------ with 3 reReads ... wait ...
#############............................................
Test result: 0 read errors

Extra info: ran for 86.35 seconds

  --- START 57 test patterns ------ with 100 reReads ... wait ...
##
Bumping from working 206 to 216 goes to Fails with no cap.
Click to expand...
Good test! Pretty cool to be able to run 205MHz without a cap. That’s good speed!
I’m hoping to reach 300MHz with the right Cap. But I’m probably just wishing to much.
 
Seems @mjs513 posted about testing that at 206 MHz - on first visit here reply was based on prior page of thread - then after posting saw this new page of the day starting before arrival ... Run of 100 ReReads completed and prior post just updated

Looking back - it runs slower at the faster clock - Again the reason for posting that 'Extra info':
for 198 MHz :: Extra info: ran for 2480.03 seconds
>> EXTMEM Memory Test, 32 Mbyte SDRAM speed 198 Mhz F_CPU_ACTUAL 600 Mhz begin@ 80000000 end@ 82000000
And for 206 MHz:: Extra info: ran for 2500.23 seconds
>> EXTMEM Memory Test, 32 Mbyte SDRAM speed 206 Mhz F_CPU_ACTUAL 600 Mhz begin@ 80000000 end@ 82000000
 
You must log in or register to reply here.
Back
Top