defragster
Senior Member+
Got this on first run of download not changing the speed with No Cap
At 206 requested this is the result: 625.73 seconds:
So no cap at that speed and no .begin() intialize.Test capacitor effect effect on SDRAM read timing margin
Clock set 254.12 MHz
Could not initialize SDRAM hardware
At 206 requested this is the result: 625.73 seconds:
Code:
Test capacitor effect effect on SDRAM read timing margin
Clock set 205.71 MHz
SDRAM hardware initialized.
This test takes approximately 5 minutes to complete.
Progress:: '#'=fixed pattern, '.'=PsuedoRand patterns, and 'F' shows Failed test pattern
If built with DUAL Serial second SerMon will show details.
--- START 57 test patterns ... wait ...
#############............................................
Test result: 0 read errors (0.0000%)
Normally no read errors is good, but for comparing the effect of your
capacitor connected to DQS (EMC_39) you need errors! When all reads are
correct, you can not know if the error-free result is because you have
good timing margin or your SDRAM reads are just barely succeeding. Only
when you see errors can you estimate your capacitor's effect on timing.
Please increase the speed and re-run this test for each capacitor. Use
a speed fast enough for all tests to give at least some errors. The
difference in number of errors allows you to gauge the relative effect
of various capacitors to choose the best capacitor for your PCB design.
Extra info: ran for 625.73 seconds
Compile Time:: C:\Users\TimLabs\Documents\GitHub\SDRAM_t4\examples\CapReadSDRAM\CapReadSDRAM.ino Jan 30 2024 17:32:51
EXTMEM Memory Test, 32 Mbyte SDRAM speed 205.71 Mhz F_CPU_ACTUAL 600 Mhz begin@ 80000000 end@ 82000000