Call to arms | Teensy + SDRAM = true

Previous post showed NXP Tech note and Perf doc link. It showed expected Write at what this is getting for 166 MHz of chip spec and same for Read speed broken out below that Combined 160 is 312 for WRITE and 108 for Read. So they are not promising any more and we are getting all of what they promise. {assuming my mathy stuff is right}.

And the write rate is as in that doc almost 3X the read rate do to something in the chip Arch or perhaps the nature of the SDRAM chip.
 
defragster said:
Previous post showed NXP Tech note and Perf doc link. It showed expected Write at what this is getting for 166 MHz of chip spec and same for Read speed broken out below that Combined 160 is 312 for WRITE and 108 for Read. So they are not promising any more and we are getting all of what they promise. {assuming my mathy stuff is right}.

And the write rate is as in that doc almost 3X the read rate do to something in the chip Arch or perhaps the nature of the SDRAM chip.
Click to expand...
So in other words, it’s all good and it’s working as it should.

So what “tasks” are left?
 
Maybe start with 4.7pF, 10pF, 15pF, and of course no capacitor. That's 4 cases to test, which becomes 12 test to run if you try each at 166, 198, 221 MHz.

Hopefully just those 12 results will show whether any further testing makes sense, and give some insight on where to focus more tests.
 
PaulStoffregen said:
Maybe start with 4.7pF, 10pF, 15pF, and of course no capacitor. That's 4 cases to test, which becomes 12 test to run if you try each at 166, 198, 221 MHz.

Hopefully just those 12 results will show whether any further testing makes sense, and give some insight on where to focus more tests.
Click to expand...
You got it! If @defragster or @mjs513 don’t test it then I will.
 
It's quite possible nothing above 166 MHz might work, no matter what is tried. The first step at 198 MHz is overclocking by 20%...

But my gut feeling is we might see the higher speeds work somewhat. And if they do, odds are good they'll be much more sensitive to C29. If it all ends up that way, the overclock tests might give us a really good idea of what C29 should ideally be. I personally think that will be a lot more interesting than just saying (as NXP's people on their forum say) that 166 MHz works without any capacitor, so end of story.
 
PaulStoffregen said:
It's quite possible nothing above 166 MHz might work, no matter what is tried. The first step at 198 MHz is overclocking by 20%...

But my gut feeling is we might see the higher speeds work somewhat. And if they do, odds are good they'll be much more sensitive to C29. If it all ends up that way, the overclock tests might give us a really good idea of what C29 should ideally be. I personally think that will be a lot more interesting than just saying (as NXP's people on their forum say) that 166 MHz works without any capacitor, so end of story.
Click to expand...
While I can test, I suspect that you will be more OCD then me when testing. So anytime you want one of these boards to play with, just give me a shout ;)
 
PaulStoffregen said:
I'm still curious to hear if 198 MHz overclock works, and whether the C29 capacitor helps or hinders?
Click to expand...
I wasn't anxious to try that - 5pF or 10pF capacitor at C29 - that was a small SMD cap and the pads are small and about a bus card thick apart.
I suppose if I have the right caps to try in 'human size' I'd try to get WW 30 gauge on the pads and solder to those.

One prior post #101 did show expected 25% Write speed BUMP going from 133 to 166 MHz - Read went up 20% - but that includes the unchanging "IF Test".

OC Bump to 198 could give another 20% ...

So what “tasks” are left?
Click to expand...
Based on directed testing so far: Everything that works - works, these tests are direct address space functional - any presented pin# from T_MM should work.
SDRAMExtMem can get coded to work - and @mjs513 may have already mapped that all out.

Much more would be a drastic Unique board config? (Min edit to 21 files and 25 places by a quick grep?) Associating all the available CPU pins to 'names' and associated edits in those and other files where pin# doesn't have the same MUX choices/features for that
bus/device' support?

If this were a final PCB with one released version of TeensyDuino that would be perhaps worthy, and good until the next TeensyDuino update was needed.

But if Dev work can use this as is until any needed known pin changes are made final maybe waiting before doing a whole edit for a Unique Board? And hack as needed in a local T_MM cores set? But @Rezo doing low level display is probably directly addressing things and may be set, perhaps just needing the SDRAMextmem::malloc() for buffers?
 
You and I can test the caps once I have a board. I’ve become quite good over the years to do small soldering. I’ll do the cap stuff here and you can guide with code? :giggle:

Since only 9 pins are sacrificed, any board made will work with this. All peripherals one could ever need are available still. So in a nutshell, no functions are sacrificed. It’s all nice and sunny!

Regarding all those files. If you use @Rezo library he made, which overrides the .ld file, no edits to the core needs to be made (from what I understand).

SDRAMExtMem, the macro stuff right?
 
@PaulStoffregen - @defragster and others

Decided after taking a break I ditch the library approach and incorporated sdram.c directly into the core like was done for tempmon_init, pwm_init etc. Think I came up with a better way to kludge it will tell more when I test it - don't want to send folks off on a wild goose chase.

But I have run into one issue. Right now in the library we make use of millis and elapsedmillis but once I include it as a .c in startup.c I get undefined errors - those functions not active yet.

Not sure how to get around that one well I do but not pretty - going to look some more.
 
If you do the initialization later, using the middle startup hook or by editing the code at that location, then all the timing functions work. You still need to be careful about use of any static instance of C++ classes that aren't designed for const init.
 
HalfCopy update working fine 32/16/8 bit with memoryCopy:
test RndSeed HalfCopy 1427530695 Write 118846 us Read/Test 252850 us
test RndSeed HalfCopy 1100533073 Write 118846 us Read/Test 252850 us
test ran for 21.52 seconds
Fixed Pattern Write ran for 1.33 and Read/Test 3.84 secs
Fixed Pattern Test 160.99 MB per sec
Fixed Pattern Test WRITES 312.57 MB per sec
Fixed Pattern Test & READ 108.41 MB per sec
PsuedoRnd Patt Write ran for 5.23 and Read/Test 11.13 secs
PsuedoRnd Patt Test 172.18 MB per sec
All memory tests passed :)
Loop doTest() count=103
Click to expand...
Made prior post EDIT with NO_CAP installed - not seeing any Errors? 18.5% BUMP in Write speed
Again: This tests a single WRITE to 32MB of the TEST values, then immediately reads back and test 5 times before calling success.
test RndSeed HalfCopy 1427530695 Write 118847 us Read/Test 237651 us
test RndSeed HalfCopy 1100533073 Write 118846 us Read/Test 237652 us
test ran for 20.20 seconds
Fixed Pattern Write ran for 1.12 and Read/Test 3.39 secs
Fixed Pattern Test 184.23 MB per sec
Fixed Pattern Test WRITES 370.79 MB per sec
Fixed Pattern Test & READ 122.57 MB per sec
PsuedoRnd Patt Write ran for 5.23 and Read/Test 10.46 secs
PsuedoRnd Patt Test 179.52 MB per sec
All memory tests passed :)
Loop doTest() count=1
Click to expand...
and three more passes later the same:
test ran for 20.20 seconds
Fixed Pattern Write ran for 1.12 and Read/Test 3.39 secs
Fixed Pattern Test 184.23 MB per sec
Fixed Pattern Test WRITES 370.79 MB per sec
Fixed Pattern Test & READ 122.57 MB per sec
PsuedoRnd Patt Write ran for 5.23 and Read/Test 10.46 secs
PsuedoRnd Patt Test 179.52 MB per sec
All memory tests passed :)
Loop doTest() count=4
Click to expand...

C: 
#define TRY198 1
#if TRY198
    const unsigned int clockdiv = 2; // PLL2_PFD2 / 2 = 396 / 2 = 198 MHz

    CCM_CBCDR = (CCM_CBCDR & ~(CCM_CBCDR_SEMC_PODF(7) | CCM_CBCDR_SEMC_ALT_CLK_SEL)) |
        CCM_CBCDR_SEMC_CLK_SEL | CCM_CBCDR_SEMC_PODF(clockdiv-1);
#else
    const unsigned int clockdiv = 4;

    CCM_CBCDR = (CCM_CBCDR & ~(CCM_CBCDR_SEMC_PODF(7))) |
        CCM_CBCDR_SEMC_CLK_SEL | CCM_CBCDR_SEMC_ALT_CLK_SEL |
        CCM_CBCDR_SEMC_PODF(clockdiv-1);
#endif
 
For anyone wanting to appreciate all the SPEW I've been watching with the edit of PSRAM to also test SDRAM:
> The '.' shows each re-read pass.
> the first 'group' are the tests in progress
> followed by Stats summary collected in the array for each test
testing with fixed pattern 5A698421 .....
testing with fixed pattern 55555555 .....
testing with fixed pattern 33333333 .....
testing with fixed pattern 0F0F0F0F .....
testing with fixed pattern 00FF00FF .....
testing with fixed pattern 0000FFFF .....
testing with fixed pattern AAAAAAAA .....
testing with fixed pattern CCCCCCCC .....
testing with fixed pattern F0F0F0F0 .....
testing with fixed pattern FF00FF00 .....
testing with fixed pattern FFFF0000 .....
testing with fixed pattern FFFFFFFF .....
testing with fixed pattern 00000000 .....
testing with pseudo-random sequence HalfCopy 8, seed=2976674124 .....
testing with pseudo-random sequence HalfCopy 32, seed=1438200953 .....
testing with pseudo-random sequence HalfCopy 16, seed=3413783263 .....
testing with pseudo-random sequence HalfCopy 8, seed=1900517911 .....
testing with pseudo-random sequence HalfCopy 32, seed=1227909400 .....
testing with pseudo-random sequence HalfCopy 16, seed=276562754 .....
testing with pseudo-random sequence HalfCopy 8, seed=146878114 .....
testing with pseudo-random sequence HalfCopy 32, seed=615545407 .....
testing with pseudo-random sequence HalfCopy 16, seed=110497896 .....
testing with pseudo-random sequence HalfCopy 8, seed=74539250 .....
testing with pseudo-random sequence HalfCopy 32, seed=4197336575 .....
testing with pseudo-random sequence HalfCopy 16, seed=2280382233 .....
testing with pseudo-random sequence HalfCopy 8, seed=542894183 .....
testing with pseudo-random sequence HalfCopy 32, seed=3978544245 .....
testing with pseudo-random sequence HalfCopy 16, seed=2315909796 .....
testing with pseudo-random sequence HalfCopy 8, seed=3736286001 .....
testing with pseudo-random sequence HalfCopy 32, seed=2876690683 .....
testing with pseudo-random sequence HalfCopy 16, seed=215559886 .....
testing with pseudo-random sequence HalfCopy 8, seed=539179291 .....
testing with pseudo-random sequence HalfCopy 32, seed=537678650 .....
testing with pseudo-random sequence HalfCopy 16, seed=4001405270 .....
testing with pseudo-random sequence HalfCopy 8, seed=2169216599 .....
testing with pseudo-random sequence HalfCopy 32, seed=4036891097 .....
testing with pseudo-random sequence HalfCopy 16, seed=1535452389 .....
testing with pseudo-random sequence HalfCopy 8, seed=2959727213 .....
testing with pseudo-random sequence HalfCopy 32, seed=4219363395 .....
testing with pseudo-random sequence HalfCopy 16, seed=1036929753 .....
testing with pseudo-random sequence HalfCopy 8, seed=2125248865 .....
testing with pseudo-random sequence HalfCopy 32, seed=3177905864 .....
testing with pseudo-random sequence HalfCopy 16, seed=2399307098 .....
testing with pseudo-random sequence HalfCopy 8, seed=3847634607 .....
testing with pseudo-random sequence HalfCopy 32, seed=27467969 .....
testing with pseudo-random sequence HalfCopy 16, seed=520563506 .....
testing with pseudo-random sequence HalfCopy 8, seed=381313790 .....
testing with pseudo-random sequence HalfCopy 32, seed=4174769276 .....
testing with pseudo-random sequence HalfCopy 16, seed=3932189449 .....
testing with pseudo-random sequence HalfCopy 8, seed=4079717394 .....
testing with pseudo-random sequence HalfCopy 32, seed=868357076 .....
testing with pseudo-random sequence HalfCopy 16, seed=2474062993 .....
testing with pseudo-random sequence HalfCopy 8, seed=1502682190 .....
testing with pseudo-random sequence HalfCopy 32, seed=2471230478 .....
testing with pseudo-random sequence HalfCopy 16, seed=85016565 .....
testing with pseudo-random sequence HalfCopy 8, seed=1427530695 .....
testing with pseudo-random sequence HalfCopy 32, seed=1100533073 .....
test Pattern 5A698421 Write 86313 us Read/Test 261085 us
test Pattern 55555555 Write 86299 us Read/Test 261085 us
test Pattern 33333333 Write 86302 us Read/Test 261085 us
test Pattern 0F0F0F0F Write 86298 us Read/Test 261086 us
test Pattern 00FF00FF Write 86301 us Read/Test 261086 us
test Pattern 0000FFFF Write 86299 us Read/Test 261086 us
test Pattern AAAAAAAA Write 86299 us Read/Test 261086 us
test Pattern CCCCCCCC Write 86301 us Read/Test 261086 us
test Pattern F0F0F0F0 Write 86301 us Read/Test 261085 us
test Pattern FF00FF00 Write 86299 us Read/Test 261086 us
test Pattern FFFF0000 Write 86300 us Read/Test 261085 us
test Pattern FFFFFFFF Write 86298 us Read/Test 261086 us
test Pattern 00000000 Write 86300 us Read/Test 261086 us
test RndSeed HalfCopy 2976674124 Write 118949 us Read/Test 237487 us
test RndSeed HalfCopy 1438200953 Write 118953 us Read/Test 237499 us
test RndSeed HalfCopy 3413783263 Write 118846 us Read/Test 237494 us
test RndSeed HalfCopy 1900517911 Write 118949 us Read/Test 237498 us
test RndSeed HalfCopy 1227909400 Write 118847 us Read/Test 237496 us
test RndSeed HalfCopy 276562754 Write 118846 us Read/Test 237504 us
test RndSeed HalfCopy 146878114 Write 118846 us Read/Test 237495 us
test RndSeed HalfCopy 615545407 Write 118846 us Read/Test 237496 us
test RndSeed HalfCopy 110497896 Write 118846 us Read/Test 237496 us
test RndSeed HalfCopy 74539250 Write 118846 us Read/Test 237492 us
test RndSeed HalfCopy 4197336575 Write 118846 us Read/Test 237509 us
test RndSeed HalfCopy 2280382233 Write 118847 us Read/Test 237495 us
test RndSeed HalfCopy 542894183 Write 118950 us Read/Test 237504 us
test RndSeed HalfCopy 3978544245 Write 118846 us Read/Test 237505 us
test RndSeed HalfCopy 2315909796 Write 118846 us Read/Test 237492 us
test RndSeed HalfCopy 3736286001 Write 118846 us Read/Test 237489 us
test RndSeed HalfCopy 2876690683 Write 118847 us Read/Test 237512 us
test RndSeed HalfCopy 215559886 Write 118846 us Read/Test 237502 us
test RndSeed HalfCopy 539179291 Write 118846 us Read/Test 237500 us
test RndSeed HalfCopy 537678650 Write 118846 us Read/Test 237498 us
test RndSeed HalfCopy 4001405270 Write 118847 us Read/Test 237503 us
test RndSeed HalfCopy 2169216599 Write 118847 us Read/Test 237499 us
test RndSeed HalfCopy 4036891097 Write 118847 us Read/Test 237517 us
test RndSeed HalfCopy 1535452389 Write 118952 us Read/Test 237481 us
test RndSeed HalfCopy 2959727213 Write 118847 us Read/Test 237500 us
test RndSeed HalfCopy 4219363395 Write 118847 us Read/Test 237500 us
test RndSeed HalfCopy 1036929753 Write 118846 us Read/Test 237516 us
test RndSeed HalfCopy 2125248865 Write 118846 us Read/Test 237526 us
test RndSeed HalfCopy 3177905864 Write 118847 us Read/Test 237527 us
test RndSeed HalfCopy 2399307098 Write 118846 us Read/Test 237504 us
test RndSeed HalfCopy 3847634607 Write 118846 us Read/Test 237517 us
test RndSeed HalfCopy 27467969 Write 118846 us Read/Test 237504 us
test RndSeed HalfCopy 520563506 Write 118846 us Read/Test 237513 us
test RndSeed HalfCopy 381313790 Write 118846 us Read/Test 237506 us
test RndSeed HalfCopy 4174769276 Write 118846 us Read/Test 237503 us
test RndSeed HalfCopy 3932189449 Write 118846 us Read/Test 237494 us
test RndSeed HalfCopy 4079717394 Write 118846 us Read/Test 237489 us
test RndSeed HalfCopy 868357076 Write 118847 us Read/Test 237483 us
test RndSeed HalfCopy 2474062993 Write 118953 us Read/Test 237489 us
test RndSeed HalfCopy 1502682190 Write 118847 us Read/Test 237496 us
test RndSeed HalfCopy 2471230478 Write 118847 us Read/Test 237504 us
test RndSeed HalfCopy 85016565 Write 118846 us Read/Test 237502 us
test RndSeed HalfCopy 1427530695 Write 118846 us Read/Test 237497 us
test RndSeed HalfCopy 1100533073 Write 118950 us Read/Test 237504 us
test ran for 20.20 seconds
Fixed Pattern Write ran for 1.12 and Read/Test 3.39 secs
Fixed Pattern Test 184.23 MB per sec
Fixed Pattern Test WRITES 370.80 MB per sec
Fixed Pattern Test & READ 122.57 MB per sec
PsuedoRnd Patt Write ran for 5.23 and Read/Test 10.45 secs
PsuedoRnd Patt Test 179.59 MB per sec
All memory tests passed :)
Loop doTest() count=7
Click to expand...
 
How do I read the SDRAM clock values to print like it did for PSRAM?
const float clocks[4] = {396.0f, 720.0f, 664.62f, 528.0f};
const float frequency = clocks[(CCM_CBCMR >> 8) & 3] / (float)(((CCM_CBCMR >> 29) & 7) + 1);
Serial.printf(" CCM_CBCMR=%08X (%.1f MHz)\n", CCM_CBCMR, frequency);
Click to expand...

Now 11 completed:
All memory tests passed :)
Loop doTest() count=11
Click to expand...
 
PaulStoffregen said:
If you do the initialization later, using the middle startup hook or by editing the code at that location, then all the timing functions work. You still need to be careful about use of any static instance of C++ classes that aren't designed for const init.
Click to expand...
hmm.... I had moved the call to after the middle hook like this:
Code: 
    analog_init();
    pwm_init();
    tempmon_init();
    startup_middle_hook();
   
//kludge for sdram
#ifdef extSDRAM
    sdram_init();
    // TODO: zero uninitialized EXTMEM variables
    // TODO: copy from flash to initialize EXTMEM variables
    sm_set_pool(&extsdram_smalloc_pool, &_extsdram_end,
        external_psram_size * 0x100000 -
        ((uint32_t)&_extsdram_end - (uint32_t)&_extsdram_start),
        1, NULL);
#endif

sdram_init() is in sdram.c (ditched the .cpp - think we talked about making it a .c earlier in the conversation.) Note its still setup as bool return though.

sdram_init() looks like:
Code: 
bool sdram_init(void)
{
    // use PLL3 PFD1 664.62 divided by 4 or 5, for 166 or 133 MHz
    // 5 = 133mhz
    // 4 = 166mhz - SDRAM rated,  see post #60
    // 3 = 221mhz
    const unsigned int clockdiv = 5;

    CCM_CBCDR = (CCM_CBCDR & ~(CCM_CBCDR_SEMC_PODF(7))) |
        CCM_CBCDR_SEMC_CLK_SEL | CCM_CBCDR_SEMC_ALT_CLK_SEL |
        CCM_CBCDR_SEMC_PODF(clockdiv-1);
       
    /* Experimental note (see https://forum.pjrc.com/index.php?threads/call-to-arms-teensy-sdram-true.73898/post-335619):
    *  if you want to try 198 MHz overclock
    *  const unsigned int clockdiv = 2; // PLL2_PFD2 / 2 = 396 / 2 = 198 MHz
    *
    *    CCM_CBCDR = (CCM_CBCDR & ~(CCM_CBCDR_SEMC_PODF(7) | CCM_CBCDR_SEMC_ALT_CLK_SEL)) |
    *    CCM_CBCDR_SEMC_CLK_SEL | CCM_CBCDR_SEMC_PODF(clockdiv-1);
    * If it doesn't work, maybe try soldering a 5pF or 10pF capacitor at C29
    */  
       
    delayMicroseconds(1);
.....

Was trying to avoid putting the configure/init code directly into startup.c like was done for psram.
and then I get :
Code: 
sdram.c:243: undefined reference to `delayMicroseconds'

Think I am mis-understanding something.... which is not unusual. But I do learn by my mistakes for the next time.
 
mjs513 said:
Was trying to avoid putting the configure/init code directly into startup.c like was done for psram.
and then I get :
Code: 
sdram.c:243: undefined reference to `delayMicroseconds'
Click to expand...
Try delayNanoseconds() ?
didn't find the source - but it may be calling micros() that has active vars dependent on millis()shared data

Found it - that isn't it - it uses CYCCNT too???
static inline void delayMicroseconds(uint32_t usec)
{
uint32_t begin = ARM_DWT_CYCCNT;
uint32_t cycles = F_CPU_ACTUAL / 1000000 * usec;
// TODO: check if cycles is large, do a wait with yield calls until it's smaller
while (ARM_DWT_CYCCNT - begin < cycles) ; // wait
}
Click to expand...

And even millis() is called right after:
tempmon_init();
startup_middle_hook();
...
while (millis() < TEENSY_INIT_USB_DELAY_BEFORE) ; // wait
Click to expand...
 
Add:
#include "core_pins.h" // delayMicroseconds()

<EDIT> BTW: 73 passes at 198 MHz
test ran for 20.20 seconds
Fixed Pattern Write ran for 1.12 and Read/Test 3.39 secs
Fixed Pattern Test 184.23 MB per sec
Fixed Pattern Test WRITES 370.79 MB per sec
Fixed Pattern Test & READ 122.57 MB per sec
PsuedoRnd Patt Write ran for 5.23 and Read/Test 10.45 secs
PsuedoRnd Patt Test 179.59 MB per sec
All memory tests passed :)
Loop doTest() count=73
Click to expand...
... changing now
test ran for 20.20 seconds
Fixed Pattern Write ran for 1.12 and Read/Test 3.39 secs
Fixed Pattern Test 184.23 MB per sec
Fixed Pattern Test WRITES 370.79 MB per sec
Fixed Pattern Test & READ 122.57 MB per sec
PsuedoRnd Patt Write ran for 5.23 and Read/Test 10.45 secs
PsuedoRnd Patt Test 179.60 MB per sec
All memory tests passed :)
Loop doTest() count=183
Click to expand...
 
Last edited:
EXTMEM is initialized before startup_middle_hook()... I think it would be consistent if SDRAM was treated the same, since people may have already written middle hooks using variables placed in extmem and may expect to be able to do the same with sdram variables (if compile-time SDRAM storage is going to be implemented).
 
Last edited:
Testing with NO-CAP and 198 MHz SDRAM showing NO FAILURES - This is now the HalfCopy for the PsueoRand that saves 16MB worth of fill - but still test running 44 unique starting seed values - just only 4M deep instead of 8M - so same testing 16 MB PSRAM got - just has a memCpy to the 2nd 16MB before testing there.

Changed the testing from repeat calls with listed values - but same values called in a loop of the same array of values - fixed and random seeds.

For some reason it has dipped under 20 seconds per complete 57 test pass of 13 Fixed values and 44 Seed to 'random':
test ran for 19.90 seconds
Fixed Pattern Write ran for 1.12 and Read/Test 3.39 secs
Fixed Pattern Test 184.23 MB per sec
Fixed Pattern Test WRITES 370.80 MB per sec
Fixed Pattern Test & READ 122.57 MB per sec
PsuedoRnd Patt Write ran for 5.23 and Read/Test 10.15 secs
PsuedoRnd Patt Test 183.10 M
Click to expand...
Wasn't sure what was easy to torment the MCU - added optional 10us ISR() (send any char(s) from SerMon and it toggles) that calcs 10 rand values and limits to 4M dwords that I read (no way to validate the ongoing expected value). That extends the test but causes no problems. Ups the overall runs time with expected impact on MB/sec rate since a test pass read or write half tales 86ms to 307ms:
test ran for 27.11 seconds
Fixed Pattern Write ran for 1.59 and Read/Test 4.47 secs
Fixed Pattern Test 137.25 MB per sec
Fixed Pattern Test WRITES 262.01 MB per sec
Fixed Pattern Test & READ 92.97 MB per sec
PsuedoRnd Patt Write ran for 7.52 and Read/Test 13.53 secs
PsuedoRnd Patt Test 133.77 MB per sec
All memory tests passed :)
Click to expand...
Next test that is easy with two labelled T_MM UARTS:
In new sketch put the current testing in an interrupt - one test at a time every ~400-500ms - but only 31MB
Have loop continuously send and receive large sets of data out each port and receive where the ports cross to each other.
Use: addMemoryForRead and addMemoryForWrite on each port with buffers in the upper 1MB of SDRAM above the test area?
Seems like an easy sketch to write and will keep the SDRAM busy with UART _ISR() sending and receiving data during the other test?

Question: (@KurtE / @PaulStoffregen): why do those hardwareserial.h addMemory()'s take size_t params when head & tail are only 16 bits?
And availableForWrite() returns signed int?
virtual int availableForWrite(void); void addMemoryForRead(void *buffer, size_t length); void addMemoryForWrite(void *buffer, size_t length); ... size_t tx_buffer_size_; size_t rx_buffer_size_; size_t tx_buffer_total_size_; size_t rx_buffer_total_size_; ... volatile uint16_t tx_buffer_head_ = 0; volatile uint16_t tx_buffer_tail_ = 0; volatile uint16_t rx_buffer_head_ = 0; volatile uint16_t rx_buffer_tail_ = 0;

I suppose a 64KB buffer for each will be enough for this test ... but I was checking before coding since there is 'extra RAM' :)

And it seems 5Mbaud is reliably usable max? Only 500KB/sec (*4?)

@mjs513 seems you are working on SDRAM_malloc? Might be handy to get valid controlled pointers with the 1062 doing the math. Will be using 5 or maybe 9 blocks for this - though they'll be single alloc. For fun I could switch up the alloc() ordering.
 
BTW @mjs513 this is the code working here for 198 MHz [ NO_CAP ] ... when set to non-zero - just switched it back to run Zzzz's hours:
Code: 
bool SDRAM_t4::init()
{
    // use PLL3 PFD1 664.62 divided by 4 or 5, for 166 or 133 MHz
    // 5 = 133mhz
    // 4 = 166mhz - SDRAM rated,  see post #60
    // 3 = 221mhz

#define TRY198 0
#if TRY198
    const unsigned int clockdiv = 2; // PLL2_PFD2 / 2 = 396 / 2 = 198 MHz

    CCM_CBCDR = (CCM_CBCDR & ~(CCM_CBCDR_SEMC_PODF(7) | CCM_CBCDR_SEMC_ALT_CLK_SEL)) |
        CCM_CBCDR_SEMC_CLK_SEL | CCM_CBCDR_SEMC_PODF(clockdiv-1);
#else
    const unsigned int clockdiv = 4;

    CCM_CBCDR = (CCM_CBCDR & ~(CCM_CBCDR_SEMC_PODF(7))) |
        CCM_CBCDR_SEMC_CLK_SEL | CCM_CBCDR_SEMC_ALT_CLK_SEL |
        CCM_CBCDR_SEMC_PODF(clockdiv-1);
#endif
 
Maybe 221 MHz?

The idea is to find an overclock speed where tuning C29 matters. But perhaps we'll hit the SDRAM chip's limits before the CPU's SDRAM interface limit. Difficult to predict, relatively simple to actually test.

Code: 
#if TRY221
    const unsigned int clockdiv = 3;

    CCM_CBCDR = (CCM_CBCDR & ~(CCM_CBCDR_SEMC_PODF(7))) |
        CCM_CBCDR_SEMC_CLK_SEL | CCM_CBCDR_SEMC_ALT_CLK_SEL |
        CCM_CBCDR_SEMC_PODF(clockdiv-1);

#elif TRY198
    const unsigned int clockdiv = 2; // PLL2_PFD2 / 2 = 396 / 2 = 198 MHz

    CCM_CBCDR = (CCM_CBCDR & ~(CCM_CBCDR_SEMC_PODF(7) | CCM_CBCDR_SEMC_ALT_CLK_SEL)) |
        CCM_CBCDR_SEMC_CLK_SEL | CCM_CBCDR_SEMC_PODF(clockdiv-1);

#else // 166 MHz
    const unsigned int clockdiv = 4;

    CCM_CBCDR = (CCM_CBCDR & ~(CCM_CBCDR_SEMC_PODF(7))) |
        CCM_CBCDR_SEMC_CLK_SEL | CCM_CBCDR_SEMC_ALT_CLK_SEL |
        CCM_CBCDR_SEMC_PODF(clockdiv-1);
#endif
 
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