change I2S BCK ratio ?

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I try to use a PCM1802 and I noticed that the output was sliced, the data coming in are sliced too (parts are missing, DOUT is outputing nothing here and there)

so I checked the BCK signal and I noticed that the teensy (3.6) outputs 32 clocks of each L/R channel (LRCK)

while the datasheet says it has to be 48 in total, 24 BCK edges per channel

is there a way to change this in the audio code library ?

here is my test code

AudioInputI2S            i2s1;           
AudioOutputAnalog        dac1;     
AudioConnection          patchCord2(i2s1, 0, dac1, 0);

#define FSYNC 12 // has to be high on normal usage

void setup() {

void loop() {

thanks in advance

Yup, you may want to read the reference manual, esp, SAI Transmit Configuration 4 Register (I2Sx_TCR4) + TCR5 - and you probable have to change the clock.
you can find the manuals here:
Would be great if you show us the code and even better if you publish it at github in a way that we can add it to the audio-library.
just checked the I2S code in the audio library, I think I am going to give up on teensy, I waste alot of time just making things work
I'll se wht I can do with a RPI zero instead
Read the PCM1802 datasheet again. 24 bits is the resolution of the L & R auto samples. That doesn't mean BCK has to equal 24 * Fs. Sections 7.4.3 and 7.4.4 (master and slave modes respectively) both say the device will work with BCK = 64 * Fs. That's exactly what Teensy audio library uses.
Read the PCM1802 datasheet again. 24 bits is the resolution of the L & R auto samples. That doesn't mean BCK has to equal 24 * Fs. Sections 7.4.3 and 7.4.4 (master and slave modes respectively) both say the device will work with BCK = 64 * Fs. That's exactly what Teensy audio library uses.
"That doesn't mean BCK has to equal 48 * Fs."
Yes, the PCM1808 works out-of-the-box with the Teensy audio library, no problem and great audio !

I do not know the differences between PCM1808 and PCM1802, however.
as for the RPI Zero W solution, audio works nice, even able to use pure data

and of course it cant be connected to my router via wlan0, maybe I broke the device when I soldered a header on it
so I can't really embed it in my instrument

why is it so god damn hard to DSP the s.. of an audio signal in 2020.... :-(

arf...I'll try to find a PCM1808...
I DID RTFM, check the image below, afaik its 24 clock bits per channel -> 48 in total, not 64

- I ordered a PCM1808

meanwhile,I fiddled around again with the PCM1802,

- I checked everything, managed to have a better input signal, allocated more audio memory
- I figured I forgot the FMT0 solder, fixed it

yet the sound is sliced here and there

here is my setup, if anyone sees something wrong (board is 5V power supplied, wiring is quiet simple (on the right)


here is an image of the two inputs, two outputs

maybe I should check for ripples on the power supply...
So, you read the manual and therefore you saw this Master Mode
In master mode, BCK and LRCK work as output pins, timing which from the clock circuit of the PCM1808 device controls these pins. The frequency of BCK is constant at 64 BCK/frame. Slave Mode
In slave mode, BCK and LRCK work as input pins. The PCM1808 device accepts 64-BCK/frame or 48BCK/frame format (only for a 384-fS system clock), not 32-BCK/frame format
while one can easily write a device driver to have 48 BCK/frame for limited MCLK (needs only to read another manual and learn how to do DMA), it clearly says 64BCK/frame.
while fig 23 and 25 clearly display 20 and 24 bits per frame
btw I use a PCM1802

I hate these discusions, I am more interested in how this can be fixed, I put a lot of work on the appliance I am building and so a lot of faith in that teensy board

yet I find myself digging the dirt once more, while I should already be writing FFT based audio effects
I even made a .NET application that is displaying my audio blocks graphicaly (I am a visual kind of guy)
sorry about that I keep editing my posts while the delete button gets clicked (FFOX issue maybe) , so I have to rewrite my whole post again
I preferred the previous forum, this one if really doddgy
For the PCM1802, the relevant text is
7.4.3 Master Mode
In master mode, BCK, LRCK, and FSYNC work as output pins, and these pins are controlled by timing which is generated in the clock circuit of the PCM1802. FSYNC is used to designate the valid data from the PCM1802. The rising edge of FSYNC indicates the starting point of the converted audio data and the falling edge of this signal indicates the ending point of the data. The frequency of this signal is fixed at 2 × LRCK. The duty cycle ratio depends on data bit length. The frequency of BCK is fixed at 64 × LRCK. The 768-fS system clock is not available in master mode.
7.4.4 Slave Mode
In slave mode, BCK, LRCK, and FSYNC work as input pins. FSYNC enables the BCK signal, and the device can shift out the converted data while FSYNC is HIGH. The PCM1802 accepts the 64-fS BCK or the 48-fS BCK format. The delay of FSYNC from the LRCK transition must be within 16 BCKs for the 64-fS BCK format and within 12 BCKs for the 48-fS BCK format.
I understand you hate this info, but the figures are only examples, in case you wanted to use 48BCK, but 64 bit is easier both for device driver and DMA.
ok thanks for lighting the way, dude ;-) people think that reading the manual is an easy task,
t's not lazyness, I am just not an english person, some datasheet are not always easy to figure

- I'll make a real PCB, eurocards are "meh" in term of soldering
- I'll try ordering another chip, maybe something's wrong with this one, I am so close to achieve my goal
Those wrong waveforms have recognizable 1-2 ms chunks of the input waveform. So focusing on clock ratios is very likely a huge distraction from the real problem.

My 2 guesses from looking at those waveforms would be not enough AudioMemory() in the code, or the PCM1802 is sending in a non-I2S format like left justified.
Look, this isn't the first time. Over and over this same conversation has come up on this forum, where someone misreads the datasheet and believes their chip expects exactly 24 BCLK clocks per phase of LRCLK. It's a common misunderstanding, because these parts of the diagrams (highlighted yellow and green) aren't always clearly explained.


Rarely are they as adamant and hostile as you've been. It almost feels like you don't want help finding the real problem.

But if you do, I want to communicate as clearly as possible that the real problem is almost certainly not the clock ratio. The sooner you can stop arguing this point and start listening to experts with a *lot* of experience on this platform, the sooner we can help you get this working. But you've just got to somehow let this wrong assumption about the problem go and let us help you to find the real cause of trouble.
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