Rezo
Well-known member
I'm building a project using DevBoard v5 (based on a Teensy Micromod schematic, with SDRAM) , and I need to access SPI instance, but the standard pins 9,10,11, 12 (B0_00, B0_01, B0_02, B0_03) are being used by the eLCDIF instance.
There is a set of alternate pins I can use (B1_03, B1_05, B1_06, B1_07), but they are not defined Teensy pins on any 4.x variant.
Looking at the hardware object for the MM/T4.0 is seems to define the pin, port and some other things:
Which is used in the SPI begin() function
I don't mind modifying the SPI library to support this, but I am having a hard time understanding what changes to make to the hardware object to allow me to use these non teensy alternate pins.
Any help would be appriciated!
There is a set of alternate pins I can use (B1_03, B1_05, B1_06, B1_07), but they are not defined Teensy pins on any 4.x variant.
Looking at the hardware object for the MM/T4.0 is seems to define the pin, port and some other things:
Code:
const SPIClass::SPI_Hardware_t SPIClass::spiclass_lpspi4_hardware = {
CCM_CCGR1, CCM_CCGR1_LPSPI4(CCM_CCGR_ON),
DMAMUX_SOURCE_LPSPI4_TX, DMAMUX_SOURCE_LPSPI4_RX, _spi_dma_rxISR0,
12,
3 | 0x10,
0,
IOMUXC_LPSPI4_SDI_SELECT_INPUT,
11,
3 | 0x10,
0,
IOMUXC_LPSPI4_SDO_SELECT_INPUT,
13,
3 | 0x10,
0,
IOMUXC_LPSPI4_SCK_SELECT_INPUT,
10,
3 | 0x10,
1,
0,
&IOMUXC_LPSPI4_PCS0_SELECT_INPUT
};Which is used in the SPI begin() function
Code:
void SPIClass::begin()
{
// CBCMR[LPSPI_CLK_SEL] - PLL2 = 528 MHz
// CBCMR[LPSPI_PODF] - div4 = 132 MHz
hardware().clock_gate_register &= ~hardware().clock_gate_mask;
CCM_CBCMR = (CCM_CBCMR & ~(CCM_CBCMR_LPSPI_PODF_MASK | CCM_CBCMR_LPSPI_CLK_SEL_MASK)) |
CCM_CBCMR_LPSPI_PODF(2) | CCM_CBCMR_LPSPI_CLK_SEL(1); // pg 714
// CCM_CBCMR_LPSPI_PODF(6) | CCM_CBCMR_LPSPI_CLK_SEL(2); // pg 714
uint32_t fastio = IOMUXC_PAD_DSE(7) | IOMUXC_PAD_SPEED(2);
//uint32_t fastio = IOMUXC_PAD_DSE(6) | IOMUXC_PAD_SPEED(1);
//uint32_t fastio = IOMUXC_PAD_DSE(3) | IOMUXC_PAD_SPEED(3);
//Serial.printf("SPI MISO: %d MOSI: %d, SCK: %d\n", hardware().miso_pin[miso_pin_index], hardware().mosi_pin[mosi_pin_index], hardware().sck_pin[sck_pin_index]);
*(portControlRegister(hardware().miso_pin[miso_pin_index])) = fastio;
*(portControlRegister(hardware().mosi_pin[mosi_pin_index])) = fastio;
*(portControlRegister(hardware().sck_pin[sck_pin_index])) = fastio;
//printf("CBCMR = %08lX\n", CCM_CBCMR);
hardware().clock_gate_register |= hardware().clock_gate_mask;
*(portConfigRegister(hardware().miso_pin[miso_pin_index])) = hardware().miso_mux[miso_pin_index];
*(portConfigRegister(hardware().mosi_pin [mosi_pin_index])) = hardware().mosi_mux[mosi_pin_index];
*(portConfigRegister(hardware().sck_pin [sck_pin_index])) = hardware().sck_mux[sck_pin_index];
// Set the Mux pins
//Serial.println("SPI: Set Input select registers");
hardware().sck_select_input_register = hardware().sck_select_val[sck_pin_index];
hardware().miso_select_input_register = hardware().miso_select_val[miso_pin_index];
hardware().mosi_select_input_register = hardware().mosi_select_val[mosi_pin_index];
//digitalWriteFast(10, HIGH);
//pinMode(10, OUTPUT);
//digitalWriteFast(10, HIGH);
port().CR = LPSPI_CR_RST;
// Lets initialize the Transmit FIFO watermark to FIFO size - 1...
// BUGBUG:: I assume queue of 16 for now...
port().FCR = LPSPI_FCR_TXWATER(15);
// We should initialize the SPI to be in a known default state.
beginTransaction(SPISettings());
endTransaction();
}I don't mind modifying the SPI library to support this, but I am having a hard time understanding what changes to make to the hardware object to allow me to use these non teensy alternate pins.
Any help would be appriciated!
