i am trying to use a Wiz850io with the T3.6 but on SPI1
i think i have changed all the things that need changing but it gets stuck in the right in the beginning when tying to read the chip type.
it seems to be this while loop in the SPIFIFO that never reaches completion
line 382 in SPIFIFO.h
any ideas is greatly appreciated
the all the changes i have made to the Ethernet an core libs are here:
https://github.com/alex-Arc/cores/tree/SPI1FIFO
https://github.com/alex-Arc/Ethernet/tree/Alternet_SPI_pin
i think i have changed all the things that need changing but it gets stuck in the right in the beginning when tying to read the chip type.
it seems to be this while loop in the SPIFIFO that never reaches completion
line 382 in SPIFIFO.h
Code:
inline void write(uint32_t b, uint32_t cont=0) __attribute__((always_inline)) {
uint32_t pcsbits = pcs1 << 16;
if (pcsbits) {
KINETISK_SPI1.PUSHR = (b & 0xFF) | pcsbits | (cont ? SPI_PUSHR_CONT : 0);
while (((KINETISK_SPI1.SR) & (15 << 12)) > (3 << 12)) ; // wait if FIFO full
} else {
*reg1 = 0;
KINETISK_SPI1.SR = SPI_SR_EOQF;
KINETISK_SPI1.PUSHR = (b & 0xFF) | (cont ? 0 : SPI_PUSHR_EOQ);
if (cont) {
while (((KINETISK_SPI1.SR) & (15 << 12)) > (3 << 12)) ;
} else {
while (!(KINETISK_SPI1.SR & SPI_SR_EOQF)){
//------------remove this------------------------
digitalWrite(13,HIGH);
delay(200);
digitalWrite(13,LOW);
delay(200);
//------------------------------------
}
*reg1 = 1;
}
}
}
any ideas is greatly appreciated
the all the changes i have made to the Ethernet an core libs are here:
https://github.com/alex-Arc/cores/tree/SPI1FIFO
https://github.com/alex-Arc/Ethernet/tree/Alternet_SPI_pin
Last edited: