xxxajk
Well-known member
I have an analog front-end pre-processor that has 4 outputs.
The outputs are pretty stupid, and signals can end up stretched.
The timing is very tight...
I could use the usual 74xxx logic to get what I need, and infact did that.
I could do it in code, but...
The CPU will be busy doing other things (sampling data), and this is time sensitive.
If I do this in code, any interrupt will affect the result.
BUT...
The FlexIO in the i.MX on Teensy 4.1 should technically be able to do what
I require without the additional hardware logic, taking up board space and increasing
the BOM costs. This is fairly easy to do on other chips that have programmable logic via state machines, again, that would increase the BOM.
Problem is there are no examples on how to do the logic mode, they're all
dealing with serial and parallel but not the logic or state machine mode.
What I have is the following signals, with a brief explanation.
Four outputs from the analog frontend:
signal SA "signal has started A"
signal SB "signal has started B"
detect DA "active low detected signal"
detect DB "active low detected signal"
The logic is as such in pseudo code:
Again, very simple, or it should be, but the processor RM isn't clear on the details...
The outputs are pretty stupid, and signals can end up stretched.
The timing is very tight...
I could use the usual 74xxx logic to get what I need, and infact did that.
I could do it in code, but...
The CPU will be busy doing other things (sampling data), and this is time sensitive.
If I do this in code, any interrupt will affect the result.
BUT...
The FlexIO in the i.MX on Teensy 4.1 should technically be able to do what
I require without the additional hardware logic, taking up board space and increasing
the BOM costs. This is fairly easy to do on other chips that have programmable logic via state machines, again, that would increase the BOM.
Problem is there are no examples on how to do the logic mode, they're all
dealing with serial and parallel but not the logic or state machine mode.
What I have is the following signals, with a brief explanation.
Four outputs from the analog frontend:
signal SA "signal has started A"
signal SB "signal has started B"
detect DA "active low detected signal"
detect DB "active low detected signal"
The logic is as such in pseudo code:
Code:
do {
do { nothing(); } while (SA == SB);
wait(~100nS); // wait for signals DA and DB to settle, filter out glitches
while (SA !=SB) {
if(DA or DB HIGH to LOW (_EDGE_) {
output_to_pin(negative_pulse(500-1000nS);
}
}
} while(1);
Again, very simple, or it should be, but the processor RM isn't clear on the details...