flexpwm and pad

D

DrM

Well-known member
Hi,

Is there a convenient way to set the pullup resistor for an output pin that is to be used with the flexpwm? The goal is that when the outen bit is cleared, the pin should remain high.

(Aside, I could simply move one of the val_n registers past the value stored in the init register so that it stops transitioning, but that takes effect after the next load.)

To be specific, I want to do this with pin 5 on a T4.

The reference manual seems ambiguous or confusing about this. Under output driver, page 952, it lists selectable pull-up/down and output keeper, but then it says these are disabled in output mode.

Thank you
 
@PaulStoffregen Thank you Paul, I will try that.

That brings up another question, how are the pins mapped to the pads. I think I found the answer in digital.c and core_pins.h. The table below is produced by grep and sort. (There seems to be a duplicate here and there, are those for some alternate configuration?)

There is one more question, about interrupt handling. Skipping ahead, I would like to have something with minimal latencyand jitter, for just one or at most two input lines.

The present implementation: It looks like you use the high speed GPIO6-9 gpios and interrupts appear on the GPIO6789 interrupt vector. Since numbered pins 0 and 1 come in on the lowest used bits (2 and 3) of the first gpio, gpio6, perhaps those have the fastest latency and smallest jitter.

Altenatively, if we are only interested in the interrupt on pins 0 and 1, would it make sense to attach to IRQ_GPIO_INT2 and IRQ_GPIO_INT3?

That is, does the gast gpio make a difference for generating interrupts, i.e. would the interrupt on gpio1_int2 really have lower latency compared to the above?

If we did this, then presumably that means we would need to set the mux too?

Thank you.


Code: 
$ for n in 6 7 8 9 ; do 
     echo "" ;
    grep GPIO${n}_DR core_pins.h | grep PORTREG | while read a b c ; do
          a=`grep ${b/PORTREG/BIT} core_pins.h  -m1` ; a="${a#* }" ; echo $b $c $a ; 
          done | sort -u | sort -nk4 ; done | grep -v PIN4[0-9] | grep -v PIN5[0-9]

CORE_PIN1_PORTREG GPIO6_DR CORE_PIN1_BIT 2
CORE_PIN0_PORTREG GPIO6_DR CORE_PIN0_BIT 3
CORE_PIN24_PORTREG GPIO6_DR CORE_PIN24_BIT 12
CORE_PIN25_PORTREG GPIO6_DR CORE_PIN25_BIT 13
CORE_PIN19_PORTREG GPIO6_DR CORE_PIN19_BIT 16
CORE_PIN39_PORTREG GPIO6_DR CORE_PIN39_BIT 16
CORE_PIN18_PORTREG GPIO6_DR CORE_PIN18_BIT 17
CORE_PIN38_PORTREG GPIO6_DR CORE_PIN38_BIT 17
CORE_PIN14_PORTREG GPIO6_DR CORE_PIN14_BIT 18
CORE_PIN15_PORTREG GPIO6_DR CORE_PIN15_BIT 19
CORE_PIN17_PORTREG GPIO6_DR CORE_PIN17_BIT 22
CORE_PIN16_PORTREG GPIO6_DR CORE_PIN16_BIT 23
CORE_PIN22_PORTREG GPIO6_DR CORE_PIN22_BIT 24
CORE_PIN23_PORTREG GPIO6_DR CORE_PIN23_BIT 25
CORE_PIN20_PORTREG GPIO6_DR CORE_PIN20_BIT 26
CORE_PIN21_PORTREG GPIO6_DR CORE_PIN21_BIT 27
CORE_PIN26_PORTREG GPIO6_DR CORE_PIN26_BIT 30
CORE_PIN27_PORTREG GPIO6_DR CORE_PIN27_BIT 31

CORE_PIN10_PORTREG GPIO7_DR CORE_PIN10_BIT 0
CORE_PIN12_PORTREG GPIO7_DR CORE_PIN12_BIT 1
CORE_PIN11_PORTREG GPIO7_DR CORE_PIN11_BIT 2
CORE_PIN13_PORTREG GPIO7_DR CORE_PIN13_BIT 3
CORE_PIN6_PORTREG GPIO7_DR CORE_PIN6_BIT 10
CORE_PIN9_PORTREG GPIO7_DR CORE_PIN9_BIT 11
CORE_PIN32_PORTREG GPIO7_DR CORE_PIN32_BIT 12
CORE_PIN37_PORTREG GPIO7_DR CORE_PIN37_BIT 12
CORE_PIN36_PORTREG GPIO7_DR CORE_PIN36_BIT 13
CORE_PIN35_PORTREG GPIO7_DR CORE_PIN35_BIT 14
CORE_PIN34_PORTREG GPIO7_DR CORE_PIN34_BIT 15
CORE_PIN8_PORTREG GPIO7_DR CORE_PIN8_BIT 16
CORE_PIN7_PORTREG GPIO7_DR CORE_PIN7_BIT 17

CORE_PIN37_PORTREG GPIO8_DR CORE_PIN37_BIT 12
CORE_PIN36_PORTREG GPIO8_DR CORE_PIN36_BIT 13
CORE_PIN35_PORTREG GPIO8_DR CORE_PIN35_BIT 14
CORE_PIN34_PORTREG GPIO8_DR CORE_PIN34_BIT 15
CORE_PIN39_PORTREG GPIO8_DR CORE_PIN39_BIT 16
CORE_PIN38_PORTREG GPIO8_DR CORE_PIN38_BIT 17
CORE_PIN28_PORTREG GPIO8_DR CORE_PIN28_BIT 18
CORE_PIN31_PORTREG GPIO8_DR CORE_PIN31_BIT 22
CORE_PIN30_PORTREG GPIO8_DR CORE_PIN30_BIT 23

CORE_PIN2_PORTREG GPIO9_DR CORE_PIN2_BIT 4
CORE_PIN3_PORTREG GPIO9_DR CORE_PIN3_BIT 5
CORE_PIN4_PORTREG GPIO9_DR CORE_PIN4_BIT 6
CORE_PIN33_PORTREG GPIO9_DR CORE_PIN33_BIT 7
CORE_PIN5_PORTREG GPIO9_DR CORE_PIN5_BIT 8
CORE_PIN29_PORTREG GPIO9_DR CORE_PIN29_BIT 31
 
Here is a more intelligible version of the table mapping pin to port register and bit, sequenced by pin number and grouped by port

Code: 
PIN      PORTREG                      BIT
0    CORE_PIN0_PORTREG   GPIO6_DR CORE_PIN0_BIT        3
1    CORE_PIN1_PORTREG   GPIO6_DR CORE_PIN1_BIT        2

2    CORE_PIN2_PORTREG   GPIO9_DR CORE_PIN2_BIT        4
3    CORE_PIN3_PORTREG   GPIO9_DR CORE_PIN3_BIT        5
4    CORE_PIN4_PORTREG   GPIO9_DR CORE_PIN4_BIT        6
5    CORE_PIN5_PORTREG   GPIO9_DR CORE_PIN5_BIT        8

6     CORE_PIN6_PORTREG   GPIO7_DR CORE_PIN6_BIT          10
7     CORE_PIN7_PORTREG   GPIO7_DR CORE_PIN7_BIT          17
8     CORE_PIN8_PORTREG   GPIO7_DR CORE_PIN8_BIT          16
9     CORE_PIN9_PORTREG   GPIO7_DR CORE_PIN9_BIT          11
10    CORE_PIN10_PORTREG   GPIO7_DR CORE_PIN10_BIT        0
11    CORE_PIN11_PORTREG   GPIO7_DR CORE_PIN11_BIT        2
12    CORE_PIN12_PORTREG   GPIO7_DR CORE_PIN12_BIT        1
13    CORE_PIN13_PORTREG   GPIO7_DR CORE_PIN13_BIT        3

14    CORE_PIN14_PORTREG   GPIO6_DR CORE_PIN14_BIT        18
15    CORE_PIN15_PORTREG   GPIO6_DR CORE_PIN15_BIT        19
16    CORE_PIN16_PORTREG   GPIO6_DR CORE_PIN16_BIT        23
17    CORE_PIN17_PORTREG   GPIO6_DR CORE_PIN17_BIT        22
18    CORE_PIN18_PORTREG   GPIO6_DR CORE_PIN18_BIT        17
19    CORE_PIN19_PORTREG   GPIO6_DR CORE_PIN19_BIT        16
20    CORE_PIN20_PORTREG   GPIO6_DR CORE_PIN20_BIT        26
21    CORE_PIN21_PORTREG   GPIO6_DR CORE_PIN21_BIT        27
22    CORE_PIN22_PORTREG   GPIO6_DR CORE_PIN22_BIT        24
23    CORE_PIN23_PORTREG   GPIO6_DR CORE_PIN23_BIT        25
24    CORE_PIN24_PORTREG   GPIO6_DR CORE_PIN24_BIT        12
25    CORE_PIN25_PORTREG   GPIO6_DR CORE_PIN25_BIT        13
26    CORE_PIN26_PORTREG   GPIO6_DR CORE_PIN26_BIT        30
27    CORE_PIN27_PORTREG   GPIO6_DR CORE_PIN27_BIT        31

28    CORE_PIN28_PORTREG   GPIO8_DR CORE_PIN28_BIT        18
29    CORE_PIN29_PORTREG   GPIO9_DR CORE_PIN29_BIT        31
30    CORE_PIN30_PORTREG   GPIO8_DR CORE_PIN30_BIT        23
31    CORE_PIN31_PORTREG   GPIO8_DR CORE_PIN31_BIT        22

32    CORE_PIN32_PORTREG   GPIO7_DR CORE_PIN32_BIT        12

33    CORE_PIN33_PORTREG   GPIO9_DR CORE_PIN33_BIT        7

34    CORE_PIN34_PORTREG   GPIO8_DR CORE_PIN34_BIT        15
35    CORE_PIN35_PORTREG   GPIO8_DR CORE_PIN35_BIT        14
36    CORE_PIN36_PORTREG   GPIO8_DR CORE_PIN36_BIT        13
37    CORE_PIN37_PORTREG   GPIO8_DR CORE_PIN37_BIT        12
38    CORE_PIN38_PORTREG   GPIO8_DR CORE_PIN38_BIT        17
39    CORE_PIN39_PORTREG   GPIO8_DR CORE_PIN39_BIT        16
40    CORE_PIN40_PORTREG   GPIO6_DR CORE_PIN40_BIT        20
41    CORE_PIN41_PORTREG   GPIO6_DR CORE_PIN41_BIT        21
42    CORE_PIN42_PORTREG   GPIO8_DR CORE_PIN42_BIT        15
43    CORE_PIN43_PORTREG   GPIO8_DR CORE_PIN43_BIT        14
44    CORE_PIN44_PORTREG   GPIO8_DR CORE_PIN44_BIT        13
45    CORE_PIN45_PORTREG   GPIO8_DR CORE_PIN45_BIT        12
46    CORE_PIN46_PORTREG   GPIO8_DR CORE_PIN46_BIT        17
47    CORE_PIN47_PORTREG   GPIO8_DR CORE_PIN47_BIT        16

48    CORE_PIN48_PORTREG   GPIO9_DR CORE_PIN48_BIT        24
49    CORE_PIN49_PORTREG   GPIO9_DR CORE_PIN49_BIT        27
50    CORE_PIN50_PORTREG   GPIO9_DR CORE_PIN50_BIT        28
51    CORE_PIN51_PORTREG   GPIO9_DR CORE_PIN51_BIT        22
52    CORE_PIN52_PORTREG   GPIO9_DR CORE_PIN52_BIT        26
53    CORE_PIN53_PORTREG   GPIO9_DR CORE_PIN53_BIT        25
54    CORE_PIN54_PORTREG   GPIO9_DR CORE_PIN54_BIT        29
 
And here are the available pin IRQs

Code: 
       IRQ_GPIO1_INT0 =        72,
        IRQ_GPIO1_INT1 =        73,
        IRQ_GPIO1_INT2 =        74,
        IRQ_GPIO1_INT3 =        75,
        IRQ_GPIO1_INT4 =        76,
        IRQ_GPIO1_INT5 =        77,
        IRQ_GPIO1_INT6 =        78,
        IRQ_GPIO1_INT7 =        79,
        IRQ_GPIO1_0_15 =        80,
        IRQ_GPIO1_16_31 =       81,
        IRQ_GPIO2_0_15 =        82,
        IRQ_GPIO2_16_31 =       83,
        IRQ_GPIO3_0_15 =        84,
        IRQ_GPIO3_16_31 =       85,
        IRQ_GPIO4_0_15 =        86,
        IRQ_GPIO4_16_31 =       87,
        IRQ_GPIO5_0_15 =        88,
        IRQ_GPIO5_16_31 =       89,
        IRQ_GPIO6789 =          157, // RT1060 only
 
with GPIO1 corresponding to the pins and bits from GPIO6 in the first table, GPIO2 for GPIO7, and so forth.
 
So, to access the interrupt for pin 0, we could mux the pin to GPIO1, and use the GPIO1_INT0 interrupt. Or we could mux it GPIO6 and use the GPIO6789 interrupt.

If we know that we only enabled one interrupt, then maybe the ISR for either case looks similar in terms of the number of ops.

If interrupts on pins 0 and 1 (bits 2 and 3) then it simplifies things to use GPIO1.

So, the question then is whether using the "fast" GPIO6 and therefore share one IRQ for the two pins, is worth the extra ops?

I suppose a reply might be "try it and see". But that will take some time. Does anybody already know the answer?
 
PaulStoffregen said:
You could try setting the PUE and PKE bits in IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, since pin 5 is pad EMC_08.

See page 569 in the reference manual.
Click to expand...


Hi Paul,

Did you mean PUS, PUE and PKE?

I found similar code in digital.c, at lines 50 and 52, and 32, and 71.

Perhaps the solution to not tri-state when using the FlexPWM and clearing the outen bit, is to simply call pinMode(INPUT_PULLUP) or pnMode(INPUT_PULLDOWN), before settting the mux for the flexpwm?

I wonder if it would be useful to add pin modes OUTPUT_PULLUP and OUTPUT__PULLDOWN?

Thanks
 
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