flexPWM pin state when output not enabled

[DrM]

Hi

For the flexpwm, we have all of the submodules running from the clock from submodule 0. Submodule 2 is running with IPOL set.

At some point in time, I want to hold the output from submodule 2, at HIGH.

First idea, try to stop submodule 2. So, setting CLDOK and clearing the RUN bit for that submodule by itself, does nothing. (Stopping all of the submodules together works okay, but stopping just one of them leaves them all running.)

Next idea, try to disenable the output from submodule 2. So, clearing the OUTEN does stop the output. But it seems to be tri-stated.

So, the question: Is there a simple way to freeze submodule 2 at its high value for a few milliseconds?

Thank you

 

[DrM]

Here is the code, in case someone is interested.

This is a header only CPP library for operating the TCD1304 with the flexPWM. This is work in progress, I need to add a few things before it will ge complete.

The relevant part of the theory operation goes like this

1) While ICG asserted, asserting SH causes charge from the photodiodes to be transferred, each pixel to its own location in the readout buffer.​

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2) With every four CLK pulses, the charges transfer to the next position in the readout buffer, and the last position transfers to the output stage.​

Here is the setup for the flexPWM (flexpwm2):

The first submodule is CLK (submodule 0)​

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The second and third are ICG and SH and run from the master clock and the master force from submodule 0.​

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The fourth submodule, we will call READ. it has no pin and runs from the master clock, at four times the period of CLK, and it has force enabled but on for its own local force bit.​

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The interrupt handler for ICG starts READ.​

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The interrupt handler for READ operats the ADC to read the pixel voltages into a buffer.​

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Some explanation:

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There are timing requirements between CLK, SH and ICG, and a somewhat looser requirement between READ and each of CLK and ICG (see tcd1304 datasheet).​

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Sharing the clock from submodule 0 seems to be necessary for keeping the submodules in sync.​

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Sharing the master force seems necessary for simultaneous start. But I have not confirmed this yet.​

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And indeed, the three submodules, CLK, SH, and ICG all start and stop as a group. Setting clkdok and clearing run for one of them seems to leave them all runnnig.​

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READ can start and stop individually.​

The problem:

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How do we stop ICG before CLK?​

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Clearing outen seems to leave the pin tri-started. Can we force the pin to stay high?​

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A perhaps minimal code for using the library might look like this in some way

  #include "TCD1304Device.h"
  #include <SPI.h>

  SPISettings spi_settings( 30000000, MSBFIRST, SPI_MODE0);   // 30 MHz, reads 1.5usecs/word including CNVST
  SPI.begin();
  SPI.beginTransaction(spi_settings);

  TCD1304Device tcd1304device = TCD1304Device();
  tcd1304device.setup_digital_pins();

  success = tcd1304device.setup(
             exposure_secs,
             pulse_width_secs,
             frame_secs,
             nframes,
             (uint16_t *) bufferpointer,
             NREADOUT,
             (void) (*send_data_callback_function)() );

  tcd1304device.start();   // call as many times as you like

​

 

[DrM]

In case you want to try it, reasonable values are (a) exposure anything from 10usecs up to 10msecs, (b) frame at least 10msecs to perhaps 20 or 40msecs, (c) pulse width 1usecs, but can be as much as 4 usecs, and (d) N at least 1.

For example, 0.01, 1.E-6, 0.01 works okay.

There are limits because the counters for the flexPWM are 16 bit. Will implement something to get past that, but for now the purpose is to get the basic functionality working.

You do not need the tcd1304 board to try it. An oscilloscope is sufficient is sufficient to see what is going on. Pins 3,4,5 for the lccd gates and 10 for the convert signal to the ADC.