Help Understanding This Code . . .

A

anatoledp

Active member
could someone help explain what this code means? I understand the overall gist that it increases the psram spi speed . . . but maybe something a little more in regards to what the 4 and 2 actually do . . . how 132mhz is calculated from that

C++: 
//Reset psram clock to 132 Mhz (default is 88mhz)
CCM_CCGR7 |= CCM_CCGR7_FLEXSPI2(CCM_CCGR_OFF);
CCM_CBCMR = (CCM_CBCMR & ~(CCM_CBCMR_FLEXSPI2_PODF_MASK | CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK)) | CCM_CBCMR_FLEXSPI2_PODF(4) | CCM_CBCMR_FLEXSPI2_CLK_SEL(2); // 528/5 = 132 MHz
CCM_CCGR7 |= CCM_CCGR7_FLEXSPI2(CCM_CCGR_ON);

the reason i ask is I was just testing different values and replacing 4 and 2 with 3 and 1 [i.e. CCM_CBCMR_FLEXSPI2_PODF(3) | CCM_CBCMR_FLEXSPI2_CLK_SEL(1)] gives a huge speed improvement in regards to psram memory latency but I dont understand what the new spi speed is with that change and more improtantly because i dont know what it really is doing if it will harm the psram or anything else on the mcu, or even if it will adversly affect something else down the line . . .

any help is appreciated
 
Here is the code from startup.c in TD 1.59. It uses (5) and (3) to set the clock to 88 MHz. I think this means that CLK_SEL(3) provides a clock of 440 MHz, and the (5) means 440/5 = 88.

Code: 
  CCM_CBCMR = (CCM_CBCMR & ~(CCM_CBCMR_FLEXSPI2_PODF_MASK
            | CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK))
            | CCM_CBCMR_FLEXSPI2_PODF(5)
            | CCM_CBCMR_FLEXSPI2_CLK_SEL(3); // 88 MHz

And here is the code from the forum that uses (4) and (2). The comment says 528/5 = 132, but it should say 528/4 = 132. So, I infer that CLK_SEL(2) provides a clock of 528 MHz. I don't know where to find documentation on the clock frequencies, but since it seems like CLK_SEL(3) = 440 MHz and CLK_SEL(2) = 528 MHz, you can play with the other number, which is the divisor. You can try various combinations to get values between 88 and 132, or you can try using smaller divisors to go above 132.

Code: 
  CCM_CBCMR = (CCM_CBCMR & ~(CCM_CBCMR_FLEXSPI2_PODF_MASK
            | CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK))
            | CCM_CBCMR_FLEXSPI2_PODF(4)
            | CCM_CBCMR_FLEXSPI2_CLK_SEL(2); // 528/5 = 132 MHz
 
joepasquariello said:
Here is the code from startup.c in TD 1.59. It uses (5) and (3) to set the clock to 88 MHz. I think this means that CLK_SEL(3) provides a clock of 440 MHz, and the (5) means 440/5 = 88.

Code: 
  CCM_CBCMR = (CCM_CBCMR & ~(CCM_CBCMR_FLEXSPI2_PODF_MASK
            | CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK))
            | CCM_CBCMR_FLEXSPI2_PODF(5)
            | CCM_CBCMR_FLEXSPI2_CLK_SEL(3); // 88 MHz

And here is the code from the forum that uses (4) and (2). The comment says 528/5 = 132, but it should say 528/4 = 132. So, I infer that CLK_SEL(2) provides a clock of 528 MHz. I don't know where to find documentation on the clock frequencies, but since it seems like CLK_SEL(3) = 440 MHz and CLK_SEL(2) = 528 MHz, you can play with the other number, which is the divisor. You can try various combinations to get values between 88 and 132, or you can try using smaller divisors to go above 132.

Code: 
  CCM_CBCMR = (CCM_CBCMR & ~(CCM_CBCMR_FLEXSPI2_PODF_MASK
            | CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK))
            | CCM_CBCMR_FLEXSPI2_PODF(4)
            | CCM_CBCMR_FLEXSPI2_CLK_SEL(2); // 528/5 = 132 MHz
Click to expand...
thanks that helps clarify and helps me to know what to start looking for . . . u dont happen to know if issues arise from increasing the clock rates do you? especially in regards to psram? also does this only affect psram or is it attached to other stuff as well?

also . . . just as a side thing since im going to assume that the flexspi speed is probably based from the cpu clock speed itself . . . wouldnt that probably infer that setting clock speed to 1 would mean the cpu speed itself? and everything below that is predefined?
 
Last edited:
The other thread seems to say that 132 MHz works, so I would just try it, and if it works, use it. I don't think you can damage the board or the PSRAM by raising that clock frequency. If you're curious, you can try running the PSRAM test program with various clock frequencies.
 
joepasquariello said:
The other thread seems to say that 132 MHz works, so I would just try it, and if it works, use it. I don't think you can damage the board or the PSRAM by raising that clock frequency. If you're curious, you can try running the PSRAM test program with various clock frequencies.
Click to expand...
yeah thats why i mentioned 3 and 1 values specifically . . . cause so far that has given me the fastest results . . . at 2 and 1 the psram no longer continues to function . . . but if my thinking is correct that 1 would be the cpu clock itself i can figure that out pretty quickly with some other tests. anyways thanks for your help . . . it has been most enlightening
 
Feedback on what works has been mixed results. Only 1 PSRAM chip made by ApMemory seems to consistently work at 132 MHz. Usually reports of 2 PSRAM chips are also successful, but I believe just a couple weeks ago we heard a report than 2 chips when using a part from Adafruit only worked up to 120 MHz. Sorry, I don't recall which of the brands Adafruit used, but it wasn't ApMemory. Maybe some searching could find that conversation or info on their site?

Reports of using a flash memory chip together with PSRAM are were we usually hear 132 MHz or other high speeds don't work. That's the main reason we still default to very conservative 88 MHz speed.
 
I was curious and have lots of test cases laying around, so I ran a few tests at132.9MHz as reported by the software using the PJRC PSRAM test combined with a simple Flash test that formats the Flash and writes/reads a file.

8MB APMemory = PASS. Test time went from 36.24 secs to 25.35 secs
16MB APMemory = PASS. Test time went from 72.5 secs to 50.68 secs
8MB APMemory + 2Gb NAND Flash = PASS
8MB APMemory + 1Gb NAND Flash = PASS
8MB APMemory + 64Mb NOR Flash = PASS

8MB ESP PSRAM64H = PASS
16MB ESP PSRAM64H = PASS

8MB Lyontek = FAIL immediately. The board also had a 64MB NOR Flash installed.

These were all different Teensy 4.1 boards and parts, so the APMemory seems solid and readily available. The original PSRAM64H also seems solid, but not sure if they are readily available anymore. I don't think the Lyontek is available anymore.

Adafruit uses 'generic' chips rated to 133MHz per their description with markings removed in their photos. Their generic datasheet is the ESP PSRAM64H, so perhaps lower bin parts? https://www.adafruit.com/product/4677

Given the performance improvement, it would be nice if it was easier to set / optimize that bus speed by the user for those wanting to optimize their setup. Maybe it's just me, but
Code: 
//Reset clock to 132 Mhz
      CCM_CCGR7 |= CCM_CCGR7_FLEXSPI2(CCM_CCGR_OFF);
      CCM_CBCMR = (CCM_CBCMR & ~(CCM_CBCMR_FLEXSPI2_PODF_MASK | CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK))
          | CCM_CBCMR_FLEXSPI2_PODF(4) | CCM_CBCMR_FLEXSPI2_CLK_SEL(2); // 528/5 = 132 MHz
      CCM_CCGR7 |= CCM_CCGR7_FLEXSPI2(CCM_CCGR_ON);
doesn't exactly roll off the tongue.
 
IIRC the PSRAM chips technically require a certain mode to be activated (burst wrap? I can't remember exactly) to guarantee 133MHz operation, and that mode isn't completely compatible with FlexSPI.
 
the ram chips im using are the adafruit "generic" ones which are either the esp-psram64 or esp-psram64h (more than likely the h varient with the clock stated ) . . . they are working fairly reliably and havnt had an issue so far with the higher clock rates. though they do seem to got out of stock fairly quickly at most places . . . but paul if ur still available since i havnt been able to run my quasi test yet to see what CCM_CBCMR_FLEXSPI2_CLK_SEL values map to . . . what is a value of 1? cause the datasheets claim the ram works at 133mhz but it is clearly capable of going over . . . and im not to sure if there is a direct way to actually get the clock speed itself. also for anyone is the ram slots run under 3.3v or 1.8v?
 
Wow, so many questions. Here's a few answers I can give quickly.

The PSRAM chips PJRC sells today are all ApMemory 6404L-3SQR. Plenty are in stock.

Years ago PJRC briefly sold some of the other parts before switching to ApMemory 6404L-3SQR.

Teensy 4.1 is designed for 3.3V I/O, including the pins to the PSRAM chip.

Overclocking and configuration & control of the frequency has been discussed many times. Several people have reported success overclocking, including on the incredibly long SDRAM thread where SDRAM overclocking was discussed. Other that this quick mention, I'm not going to go into overclocking any further. If you really want it, hopefully knowing conversations exist on this forum will help you search.
 
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