Is it possible to collect data from external ADC by parallel 16-bits at teensy 4.1?

W

was-ja

Well-known member
Hello,

I have an ADC like https://www.microchip.com/en-us/product/MCP37D31-80 with parallel CMOS and want to collect data from this ADC into Teensy 4.1 and perform computations on fly. I have tested computations and it seems that they are duable with teensy 4.1, but I need data to be transferred over DMA into the teensy 4.1, so that I can use processor performance in parallel with the data transfer. AFAIK, 80MHz@16bits maps to 1/16 clock per word and should be achievable on DMA.

Short look forwarded me to FlexIO, but I have not found any example for reading, only to writing.

Please, suggest me is it possible to collect parallel 16 bit data at 40-60-80MHz speed, and if yes, please, if possible share an example, or suggest what to use.

Thank you!
 
The 16 bits you have available on FlexIO3 do not support DMA transfers unfortunately.
You can try an interrupt driven method where you can fill up four 32 bit FlexIO buffers with data and transfers that to RAM/SD/Flash or wherever it needs to be.
This will give you some overhead to do other things with the cpu thread.
 
Thank you very much for the replays. Ok, it seems that it will be easy for me to use alternative external ADC with shorter parallel bus to fit into FlexIO2 with DMA, as, for example, afe5401 (12 bits) or LM98714 (8 bits). Hope that I can achieve fast clocks, like 40-50MHz, otherwise it is not too attractive for my application - with 16bits@20MHz I can transfer data from ADCs to several other boards alternatives, including extremely cheap esp32.
 
You can get 8 consecutive bits on FlexIO2 on a Teensy Micromod.
On the T4.1 you might be able to achieve 8 bits but they are scattered over a 32 bit register.
So you would have to do bit shifting to convert the data into the appropriate sized buffer - I don’t know how efficient that would be for fast data processing
 
I'd try for 16 bits wide on FlexIO3. Internally FlexIO can capture 8 shift registers of 32 bit, so you'll be looking at 1 interrupt for every 16 ADC samples. At 25 MHz, that's just under 1.6 million interrupts per second. You'll burn quite a bit of CPU time compared with DMA, but it should be doable.

8 bits on FlexIO2 with DMA might also be possible, but that will add the difficult step of dealing which which half if the MBS vs LSB. FlexIO is tricky to understand, so I'd go with simpler 16 bits wide and take a hit with the CPU time for 1.6 million interrupts/sec.

But this really is pushing the limits of what Teensy 4 can do. You might have an easier time using a FPGA. I see page 126 of the MCP37D31 datasheet has a capture card which appears to have a Xilinx FPGA.

I'm also curious if you're planning to make your own PCB for this MCP37D31 chip, and if so, have to started the design yet? Page 134 shows the BGA pitch is 0.65 mm, which is the same as Teensy 4.0. The pinout on page 5 looks like all the real signals on located on the outside 2 edges of balls, which should make the escape routing reasonable. But still, 0.65 mm pitch is tough. Wondering what your PCB plan looks like?

EDIT: another minor detail is the I/O voltage. Looks like MCP37D31 uses 1.8 volt signals. Teensy is configured for 3.3 volts. We did get the HM01B0 to work with 1.8V signals feeding into the 3.3V pins, but that's very little noise margin and probably doesn't give the full timing. The HM01B0 signals were relatively slow speed. Maybe you can use level shifters, but they add delay which could really make this more complicated if the delays for each pin are well matched. You might be looking at needing to make a DIY Teensy PCB using the bootloader chip, where you'd wire 1 or more banks of the GPIO pins to use 1.8V power. So many aspects of this project are difficult because you're pushing the limits... but no amount of creating FlexIO config and efficient software will make up for the signals not arriving properly.
 
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Thank you very much, Rezo and PaulStoffregen, for your kind comments!

Yes, seems that FlexIO3 is still doable. I will probably mix my numerics with FlexIO, probably I can save interrupts here, to save some takts. I also have experienced to run several Teensy 4.1 boards 24/7 at 816MHz for weeks without any failure, so, it give me a little bit more efforts. Indeed I used heavy copper heat-sink.

Regarding to MCP37D31 - yes, it also doable to rote it at just 2-l PCB with 0.1mm/0.1mm traces/distances and 0.2mm vias, I did it ones :) It is really simple chip, but 2-l is crazy, and 4-l are not so expensive. I have also alternative for ADC as afe5401 with has more convenient digital IO voltages.

Almost ten previous years, I coupled fast ADCs (25-400MHz) with FPGA running numerics on FPGA and forwarding the results at MCU, and I really hate to do it. Please, understand me.

So, when I see first Teensy 4.1 and have measured its fast GPIO that I can drive at 2.5ns speed, I really trying to port my ADC-FPGA hardware to ADC-MCU.

Regarding to 1.8V at MCP37D31 it may be an issue, but I had already experience to use this chip at 2V of digital IO, so, it again duable without level shifters.
 
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