BertG
New member
Hi,
we are using Teensy4.1 with a LPSPI connection to a WIZNET805IO (WIZNET5500 chip) module. For some reason every data byte sent (data bits and 8 clock cycles on the logic are ok, timing is perfect) is followed by another 8 clock cycles with MOSI staying at HIGH level which confuses the WIZNET. Using a bit-banger and simulating same data stream the WIZNET responds as expected. Probably a problem with the configuration of the SPI channel. We use SPI.h and SPI.cpp. Any ideas?
we are using Teensy4.1 with a LPSPI connection to a WIZNET805IO (WIZNET5500 chip) module. For some reason every data byte sent (data bits and 8 clock cycles on the logic are ok, timing is perfect) is followed by another 8 clock cycles with MOSI staying at HIGH level which confuses the WIZNET. Using a bit-banger and simulating same data stream the WIZNET responds as expected. Probably a problem with the configuration of the SPI channel. We use SPI.h and SPI.cpp. Any ideas?