MCLK and I2S

[DiamondDrake]

Is it possible to use the MCLK output on pin 12 for an arbitrarily clock output while using the I2S/SAI peripheral in slave mode? Its not clear from the datasheet or the user guide if this is possible but I can't seem to get it to work.

I can't actually get the MCLK to output a signal at all unless using the audio library, So I'm wondering if MCLK only works when the I2s interface is fully initialized.

 

[PaulStoffregen]

I do not know if MCLK works when you use slave mode.

But I do know it's possible to turn on MCLK without initializing the rest of the I2S stuff.

 

[DiamondDrake]

I do not know if MCLK works when you use slave mode.

But I do know it's possible to turn on MCLK without initializing the rest of the I2S stuff.

The datasheet makes it appear as though that is the case, But for some reason it doesn't seem to be activating.

#define MCLK_SRC 3
#define MCLK_MULT 2
#define MCLK_DIV 17
// enable MCLK output
I2S0_MCR = I2S_MCR_MICS(MCLK_SRC) | I2S_MCR_MOE; //choose src - MOE is enable output
while (I2S0_MCR & I2S_MCR_DUF) ;
I2S0_MDR = I2S_MDR_FRACT((MCLK_MULT-1)) | I2S_MDR_DIVIDE((MCLK_DIV-1)); //set dividers

As far as I can tell from the datasheet, this (exert from the audio lib) seems like it would be all you need you, but it doesn't seem to do anything (outside of using the audio library).

 

[WMXZ]

The datasheet makes it appear as though that is the case, But for some reason it doesn't seem to be activating.

#define MCLK_SRC 3
#define MCLK_MULT 2
#define MCLK_DIV 17
// enable MCLK output
I2S0_MCR = I2S_MCR_MICS(MCLK_SRC) | I2S_MCR_MOE; //choose src - MOE is enable output
while (I2S0_MCR & I2S_MCR_DUF) ;
I2S0_MDR = I2S_MDR_FRACT((MCLK_MULT-1)) | I2S_MDR_DIVIDE((MCLK_DIV-1)); //set dividers

As far as I can tell from the datasheet, this (exert from the audio lib) seems like it would be all you need you, but it doesn't seem to do anything (outside of using the audio library).

you have to 'activate' the I2S lines including the MCLK (here for T3.2 with only one MCLK);
something like

		CORE_PIN9_CONFIG  = PORT_PCR_MUX(6); // pin 9,  PTC3, I2S0_TX_BCLK
		CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK
		CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS
		CORE_PIN13_CONFIG = PORT_PCR_MUX(4); // pin 13, PTC5, I2S0_RXD0

BTW, check datasheet if MCLK is also on pin12, On T3.2 it is only on Pin 11

 

[DiamondDrake]

you have to 'activate' the I2S lines including the MCLK (here for T3.2 with only one MCLK);
something like

                CORE_PIN9_CONFIG  = PORT_PCR_MUX(6); // pin 9,  PTC3, I2S0_TX_BCLK
		CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK
		CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS
		CORE_PIN13_CONFIG = PORT_PCR_MUX(4); // pin 13, PTC5, I2S0_RXD0

BTW, check datasheet if MCLK is also on pin12, On T3.2 it is only on Pin 11

Thank you!
I did mean pin 11, I forget that the GND pin doesn't have a number associated with it. That was part of the problem, but also, there is one more line I needed to make it work.

SIM_SCGC6 |= SIM_SCGC6_I2S;

According to the Teensy Core This is how it's defined:

#define SIM_SCGC6		(*(volatile uint32_t *)0x4004803C) // System Clock Gating Control Register 6
#define SIM_SCGC6_I2S			((uint32_t)0x00008000)		// I2S Clock Gate Control

This sets the I2S clock enable bit in the System Clocks Gating Control Register 6.
It very vaguely states "This bit controls the clock gate to the I2S module" in the userguide version of the datasheet.

Its not clear if having this enabled would prevent slave I2S, since there is very little in the way of guidance in the chip's user guide, it's more like a reference than a guide.

 

[WMXZ]

Thank you!
I did mean pin 11, I forget that the GND pin doesn't have a number associated with it. That was part of the problem, but also, there is one more line I needed to make it work.

SIM_SCGC6 |= SIM_SCGC6_I2S;

According to the Teensy Core This is how it's defined:

#define SIM_SCGC6		(*(volatile uint32_t *)0x4004803C) // System Clock Gating Control Register 6
#define SIM_SCGC6_I2S			((uint32_t)0x00008000)		// I2S Clock Gate Control

This sets the I2S clock enable bit in the System Clocks Gating Control Register 6.
It very vaguely states "This bit controls the clock gate to the I2S module" in the userguide version of the datasheet.

Its not clear if having this enabled would prevent slave I2S, since there is very little in the way of guidance in the chip's user guide, it's more like a reference than a guide.

that is correct, clock must be enabled. This is valid for all peripherals.