The basic idea is the update() function takes the 128 audio samples from incoming blocks and copies them to a buffer in the order they'll need to be written to the PWM hardware.
Then the ISR does a DMA transfer with that buffer as the source and the PWM registers as the destination. I believe the PWM registers have control/status registers between them, so you'll need to configure the DMA to increment more than 4 bytes as it does each write, so it ends up writing the audio onto the DMA registers.
The existing PWM code actually does something similar, where it puts PWM output for both pins 3 and 4, for the MSB and LSB of the data. In theory, both can be combined with resistors for 16 bit output. In practice, even 0.1% matched resistors give only about 10-11 bits, and the resistors are in series with the output impedance (approx 16 to 20 ohms) of the transistors in the chip. But the code is already there to output 2 PWM streams, so a first easy step would be converting the already-working DMA code to output stereo instead of 2 streams computed from a single input.
There's also a minor issue of the DMA trigger happening by the compare match that generates the PWM, which means you can't write a zero (no match ever happens) and you can't write numbers very close to the max (not enough time for the trigger cause another transfer before the next PWM waveform). Look at the PWM code, which converts the audio to a limited range of the PWM duty cycle. The range can be expanded a bit, as I was quite conservative for a 1.0 release, but beware zero and triggering the DMA too close to the end of the cycle.
I'm currently working on another really important project, so I can't get directly involved in the coding at this time. Hopefully this message will help get you started?
