new design, flexio, four in, 1 out


Well-known member
Hi, I am about to start a new design using the Teensy 4.0. I would like to ask and double check that it is realistic and feasible.

The board will have four ADC's and one DAC. The five devices would be connected to five pins. They clock would go to all five in parallel. So, we would have four lines with bits coming in and one line with bits going out. Ideally, we would like to do this at 50 MHz.

This will be a general purpose DAQ with simultaneous 16 bit inputs and one output, hopefully at 1 MHz.

Is that feasible and realistic with the Flex IO? Is there a better way to do it?

Thank you
Creating a custom FlexIO peripheral can be a tough nut to crack. I've done it only once from scratch... and it wasn't easy. NXP's documentation leaves a lot to be desired.

Unless someone chimes in with a FlexIO library or code which achieves this particular setup, you're probably going to have to dive into that NXP documentation. It's chapter 50 of the reference manual starting on page 2943.

Hi Paul, thanks. The piece from miciwan, makes it seem almost easy. I think I understand how to setup the shifters. But so far I haven't see a clear description of how to set up the clock. The example in miciwan's guide, 12 bit wide parallel, is far too complicated to be helpful. If the wiki would show a simpler example, a single stream, and then one with two parallel streams maybe one in and one out, then I think we would all have a better starting point. Maybe KurtE has that in his library, I have not tarted to look at it closely yet.