Non-volatile alternatives for PSRAM.

The address isn't configurable, it's fixed for each FlexSPI instance.
If writing was going to be done with direct memory access (rather than FlexSPI IP commands like LittleFS currently does) the MPU region mode would probably have to be changed to cached write-through, so reads would still be cached but writes would be pushed as they happened rather than delayed.
 
FLASH = the default flash, connected to FlexSPI1, fixed @ 0x60000000
ERAM = optional PSRAM and/or flash chip (or MRAM in this case), connected to FlexSPI2, fixed @ 0x70000000
 
... bit of a puzzle - but three media types and only two slots ...
PSRAM can span #1 or #1 and #2 and Flash only on #2
 
Each FlexSPI can theoretically connect up to 4 memory chips. See Figure 27-2 on page 1604 in the reference manual.

Teensy 4.1 physically has wiring to connect only 1 chip (the main program memory) to FlexSPI1, and 2 chips (the bottom side QSPI pads) to FlexSPI2.

Chips connected to FlexSPI1 are mapped to the range 60000000 to 6FFFFFFF. Chips connected to FlexSPI1 are mapped to the range 70000000 to 7EFFFFFF. To confirm, see Table 3-1 on page 35.

Where each chip appears within the possible address range depends on the FlexSPI configuration. FlexSPI is documented in Chapter 27, starting on page 27. For a summary, you might start reading at 27.3.4 "Flash memory map" starting on page 1608.

FlexSPI provides 2 interfaces to the memory. See Figure 27-1 "FlexSPI block diagram". Any chip can be accessed with either interface. In practice, we use the AHB bus (memory mapped) for main flash and PSRAM. LittleFS uses IPS bus for the QSPI flash.

If you want to talk of what can done, please read the relevant parts of the reference manual.
 
Never mind then. I'll just stick to using my own linker script and FlexSPI2 initialization code (which enabling prefetching, something I filed a PR for nearly 18 months ago) if I'm going to be told to go RTFM when I clearly already have.
 
These ref manual pages are mostly about which chips can be in which memory regions.

Cache config isn't covered anywhere (as far as I know) in NXP's reference manual, since it come from the ARM MPU.
 
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