whitelightning
New member
Hi everyone,
I’m working on a project using the Teensy 4.1, and I’m trying to generate two pairs of complementary PWM signals for driving MOSFET driver circuits.
My goal:
Use FLEXPWM2 submodules SM0 and SM2, both channels A and B.
Generate PWM at 1 MHz frequency, 50% duty cycle.
Add ~50 ns dead time between A and B in each submodule.
Invert the polarity of both outputs relative to their default.
Outputs mapped as follows:
I want:
What I’ve tried:
My problems:
My questions:
Does anyone have working code examples (register-level or using libraries) that:
Is there any special clock gating or IOMUX setup required beyond CCM_CCGR4 and the SW_MUX registers?
Is there a reliable way to invert PWM polarity purely in registers for FLEXPWM2 SM0 and SM2?
I’ve been working on this for a couple of weeks and keep hitting roadblocks. Any examples, code snippets, or insights would be hugely appreciated!
Thanks so much for your help.
I’m working on a project using the Teensy 4.1, and I’m trying to generate two pairs of complementary PWM signals for driving MOSFET driver circuits.
My goal:
- SM0 (FLEXPWM2_SM0):
- Pin 4 → FLEXPWM2_PWM0_A
- Pin 33 → FLEXPWM2_PWM0_B
- SM2 (FLEXPWM2_SM2):
- Pin 6 → FLEXPWM2_PWM2_A
- Pin 9 → FLEXPWM2_PWM2_B
I want:
- A and B channels on each submodule to be complementary (when A is HIGH → B is LOW and vice versa).
- ~50 ns dead time between switching.
- All outputs inverted relative to default polarity.
What I’ve tried:
- eFlexPWM library – but it doesn’t expose polarity inversion or direct register access for FLEXPWM2 SM0 and SM2.
- Direct register-level programming based on the IMXRT1060 reference manual.
- Reading PJRC forum posts about using OCTRL, DTCNT0/1, and OUTEN registers.
- Manually configuring mux registers to route the PWM outputs to the desired pins.
My problems:
- I can’t get output signals on pins 4, 33, 6, and 9 with my register-level code.
- I’m not sure if I’m correctly enabling clocks and setting CCM_CCGR4 for FLEXPWM2.
- I’m unclear on the proper way to invert the polarity of SM0 A/B and SM2 A/B outputs.
- I’m confused about the necessary IOMUXC_SW_MUX and SW_PAD settings for routing PWM2 SM0 and SM2 outputs to the correct pins.
My questions:
- Enable FLEXPWM2 properly.
- Configure both SM0 and SM2 for 1 MHz PWM, 50% duty.
- Set ~50 ns dead time for each submodule.
- Invert output polarity for channels A and B.
- Drive signals to pins 4, 33, 6, and 9.
I’ve been working on this for a couple of weeks and keep hitting roadblocks. Any examples, code snippets, or insights would be hugely appreciated!
Thanks so much for your help.