Yo guys! I've been tinkering with something on my Teensy 4.1 and realized something that might interest you. So, you know when you're working on projects that require signal reactivity, latency and all that, there's something that bugs me about the use of high-frequency parallel ports. Has anyone ever tried to push the frequency to the max on the parallel bus (like 100 MHz) with the Teensy 4.1? I'm testing this for a personal project, and it seems to be getting a bit hot, but I'm not sure if that's normal or if I'm doing something wrong.
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Optimizing performance with Teensy 4.1
- Thread starter Phoebe1
- Start date
I run an 8 bit parallel bus at up to 120 MHz while running the processor at 528 MHz.
I'm using FlexIO hardware to do the IO side of things.
If you are changing multiple IO pins at a high speeds then power draw (and so temperature) is going to be higher, you're having to push a lot more current through those IO pins in order to constantly charger/discharge the capacitance on those lines.
I'm using FlexIO hardware to do the IO side of things.
If you are changing multiple IO pins at a high speeds then power draw (and so temperature) is going to be higher, you're having to push a lot more current through those IO pins in order to constantly charger/discharge the capacitance on those lines.
Its the CMOS power consumption equation, P = nfCV^2, where n is the number of signals, f is the frequency they change at, C is the capacitance per signal, V is the supply voltage.
So 8 signals at 100MHz driving 20pF at 3.3V must dissipate at least 175mW or so.
This is why LVDS is used for fast signals, the V is much smaller, so V^2 is even smaller.
On chip the capacitances are measured in femtofarads, so the I/O can dominate power consumption even though the number of signals is a lot less - PCB stray capacitances are orders of magnitude larger than on-chip, and I/O voltage is often much larger than Vcore.
So 8 signals at 100MHz driving 20pF at 3.3V must dissipate at least 175mW or so.
This is why LVDS is used for fast signals, the V is much smaller, so V^2 is even smaller.
On chip the capacitances are measured in femtofarads, so the I/O can dominate power consumption even though the number of signals is a lot less - PCB stray capacitances are orders of magnitude larger than on-chip, and I/O voltage is often much larger than Vcore.