PaulStoffregen
Well-known member
While we wait for the amazing 1170 chip, I'm considering making another Teensy4 with the same 1062 chip we have on Teensy 4.0, but in the Teensy 3.6 form factor.
So let's talk in this thread of which pins to (hypothetically) make available.
We would get 18 more pins on the outside edge, and maybe more on the bottom. Very likely the first 10 should be the same pins as we have on the bottom of Teensy 4.0? That would allow only 8 more pins. Or maybe all 18 could be chosen for this board. Only the 28 pins matching Teensy 4.0 have to be preserved.
These are all the unconnected pins on Teensy 4.0 which could become available:
I am considering putting an ethernet PHY chip on this board, with 6 pins/pads to connect another board having the magnetics and RJ45 connector. Or if a PHY chip isn't used, perhaps a high density connector with the RMII signals? Either way, I'm leaning towards reserving B1_04 to B1_11, and B1_14 & B1_15 for native ethernet.
Another feature I'm considering is using the bottom side for locations to add 1 or 2 QSPI memory chips, which could be either flash or psram. If that is done, pins EMC_22 to EMC_29 would likely be used. An alternative would be EMC_10 to EMC16, which supports only a single memory chip (only 1 chip select).
I know JTAG is going to come up. Let me say right now, access to JTAG signals will *not* happen for this board (if this board is even made). Please don't fill this thread with talk of JTAG debug. Yes, I know so many people have strong feelings about this. I do have long-term plans there. But this board, if it gets made, is meant to be a "quick" design that mostly leverages all the work that's gone into Teensy 4.0, to give access to pins & peripherals we couldn't get from Teensy 4.0's small form factor. That means no changes to the bootloader or programming approach. Changing any of that would almost certainly cause developing this board to drag on and on, pulling engineering time away from 1170 next year. So no JTAG.
Please remember this thread is about what pins (from this list) to bring out, and possibly what relatively small & low-risk peripheral hardware might fit nicely in the extra space we get.
So let's talk in this thread of which pins to (hypothetically) make available.
We would get 18 more pins on the outside edge, and maybe more on the bottom. Very likely the first 10 should be the same pins as we have on the bottom of Teensy 4.0? That would allow only 8 more pins. Or maybe all 18 could be chosen for this board. Only the 28 pins matching Teensy 4.0 have to be preserved.
These are all the unconnected pins on Teensy 4.0 which could become available:
Code:
Name BGA Analog ATL0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9
---- --- ------ ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
AD_B0_00 M14 PWM2_A3 XBAR_INOUT14 REF_CLK_32K USB_OTG2_ID I2C1_SCLS GPIO1:0 USDHC1_RESET_B SPI3_SCK
AD_B0_01 H10 PWM2_B3 XBAR_INOUT15 REF_CLK_24M USB_OTG1_ID I2C1_SDAS GPIO1:1 EWM_OUT_B SPI3_MOSI
AD_B0_14 H14 A1:3 USB_OTG2_OC XBAR_IN24 UART1_CTS ENET1588_OUT0 CSI_VSYNC GPIO1:14 CAN2_TX wdog1_any FLEXCAN3_TX
AD_B0_15 L10 A1:4 USB_OTG2_PWR XBAR_IN25 UART1_RTS ENET1588_IN0 CSI_HSYNC GPIO1:15 CAN2_RX WDOG1_RST_B_DEB FLEXCAN3_RX
AD_B1_04 L12 A1:9 FLEXSPI_B_DATA3 ENET_MDC UART3_CTS SPDIF_SR_CLK CSI_PIXCLK GPIO1:20 USDHC2_DATA0 KPP_ROW5 GPT2_CAPTURE2 FlexIO3:4
AD_B1_05 K12 A1:10 FLEXSPI_B_DATA2 ENET_MDIO UART3_RTS SPDIF_OUT CSI_MCLK GPIO1:21 USDHC2_DATA1 KPP_COL5 GPT2_COMPARE1 FlexIO3:5
AD_B1_12 H12 A2:1 FLEXSPI_A_DATA1 ACMP_OUT00 SPI3_PCS0 SAI1_RX0 CSI_DATA05 GPIO1:28 USDHC2_DATA4 KPP_ROW1 ENET21588_OUT2 FlexIO3:12
AD_B1_13 H11 A2:2 FLEXSPI_A_DATA0 ACMP_OUT01 SPI3_MISO SAI1_TX0 CSI_DATA04 GPIO1:29 USDHC2_DATA5 KPP_COL1 ENET21588_IN2 FlexIO3:13
Name BGA ATL0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9
---- --- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
B0_04 C8 LCD_DATA00 QTIMER2_TIMER1 I2C2_SCL ARM_TRACE0 FlexIO2:4 GPIO2:4 SRC_BOOT_CFG00 ENET2_TDATA03
B0_05 B8 LCD_DATA01 QTIMER2_TIMER2 I2C2_SDA ARM_TRACE1 FlexIO2:5 GPIO2:5 SRC_BOOT_CFG01 ENET2_TDATA02
B0_06 A8 LCD_DATA02 QTIMER3_TIMER0 PWM2_A0 ARM_TRACE2 FlexIO2:6 GPIO2:6 SRC_BOOT_CFG02 ENET2_RX_CLK
B0_07 A9 LCD_DATA03 QTIMER3_TIMER1 PWM2_B0 ARM_TRACE3 FlexIO2:7 GPIO2:7 SRC_BOOT_CFG03 ENET2_TX_ER
B0_08 B9 LCD_DATA04 QTIMER3_TIMER2 PWM2_A1 UART3_TX FlexIO2:8 GPIO2:8 SRC_BOOT_CFG04 ENET2_RDATA03
B0_09 C9 LCD_DATA05 QTIMER4_TIMER0 PWM2_B1 UART3_RX FlexIO2:9 GPIO2:9 SRC_BOOT_CFG05 ENET2_RDATA02
B0_14 E10 LCD_DATA10 XBAR_INOUT12 ARM_CM7_EVENT0 SAI1_RX_SYNC FlexIO2:14 GPIO2:14 SRC_BOOT_CFG10 ENET2_TX_EN
B0_15 E11 LCD_DATA11 XBAR_INOUT13 ARM_CM7_EVENT1 SAI1_RX_BCLK FlexIO2:15 GPIO2:15 SRC_BOOT_CFG11 ENET2_TX_CLK ENET2_REF_CLK2
B1_02 C11 LCD_DATA14 XBAR_INOUT16 SPI4_CS2 SAI1_TX_BCLK FlexIO2:18 GPIO2:18 PWM2_A3 ENET2_RDATA01 FlexIO3:18
B1_03 D11 LCD_DATA15 XBAR_INOUT17 SPI4_CS1 SAI1_TX_SYNC FlexIO2:19 GPIO2:19 PWM2_B3 ENET2_RX_EN FlexIO3:19
B1_04 E12 LCD_DATA16 SPI4_CS0 CSI_DATA15 ENET_RX_DATA0 FlexIO2:20 GPIO2:20 - - GPT1_CLK FlexIO3:20
B1_05 D12 LCD_DATA17 SPI4_MISO CSI_DATA14 ENET_RX_DATA1 FlexIO2:21 GPIO2:21 - - GPT1_CAPTURE1 FlexIO3:21
B1_06 C12 LCD_DATA18 SPI4_MOSI CSI_DATA13 ENET_RX_EN FlexIO2:22 GPIO2:22 - - GPT1_CAPTURE2 FlexIO3:22
B1_07 B12 LCD_DATA19 SPI4_SCK CSI_DATA12 ENET_TX_DATA0 FlexIO2:23 GPIO2:23 - - GPT1_COMPARE1 FlexIO3:23
B1_08 A12 LCD_DATA20 QTIMER1_TIMER3 CSI_DATA11 ENET_TX_DATA1 FlexIO2:24 GPIO2:24 CAN2_TX - GPT1_COMPARE2 FlexIO3:24
B1_09 A13 LCD_DATA21 QTIMER2_TIMER3 CSI_DATA10 ENET_TX_EN FlexIO2:25 GPIO2:25 CAN2_RX - GPT1_COMPARE3 FlexIO3:25
B1_10 B13 LCD_DATA22 QTIMER3_TIMER3 CSI_DATA00 ENET_TX_CLK FlexIO2:26 GPIO2:26 ENET_REF_CLK - FlexIO3:26
B1_11 C13 LCD_DATA23 QTIMER4_TIMER3 CSI_DATA01 ENET_RX_ER FlexIO2:27 GPIO2:27 SPI4_CS3 - FlexIO3:27
B1_12 D13 - UART5_TX CSI_PIXCLK ENET1588_IN0 FlexIO2:28 GPIO2:28 USDHC1_CD_B - FlexIO3:28
B1_13 D14 WDOG1_B UART5_RX CSI_VSYNC ENET1588_OUT0 FlexIO2:29 GPIO2:29 USDHC1_WP - SEMC_DQS4 FlexIO3:29
B1_14 C14 ENET_MDC PWM4_A2 CSI_HSYNC XBAR_IN02 FlexIO2:30 GPIO2:30 USDHC1_VSELECT - ENET2_TDATA00 FlexIO3:30
B1_15 B14 ENET_MDIO PWM4_A3 CSI_MCLK XBAR_IN03 FlexIO2:31 GPIO2:31 USDHC1_RESET_B - ENET2_TDATA01 FlexIO3:31
Name BGA ATL0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9
---- --- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
EMC_00 E3 SEMC_DATA00 PWM4_A0 SPI2_SCK XBAR_IN02 FlexIO1:0 GPIO4:0 USB_PHY1_TSTI_TX_LS_MODE
EMC_02 F4 SEMC_DATA02 PWM4_A1 SPI2_MOSI XBAR_INOUT04 FlexIO1:2 GPIO4:2 USB_PHY1_TSTI_TX_DN
EMC_03 G4 SEMC_DATA03 PWM4_B1 SPI2_MISO XBAR_INOUT05 FlexIO1:3 GPIO4:3 USB_PHY1_TSTO_RX_SQUELCH
EMC_09 C2 SEMC_ADDR00 PWM2_B1 SAI2_RX_SYNC CAN2_TX FlexIO1:9 GPIO4:9 USB_PHY1_TSTI_TX_EN
EMC_10 G1 SEMC_ADDR01 PWM2_A2 SAI2_RX_BCLK CAN2_RX FlexIO1:10 GPIO4:10 USB_PHY1_TSTI_TX_HIZ FLEXSPI2_B_SS0_B
EMC_11 G3 SEMC_ADDR02 PWM2_B2 I2C4_SDA USDHC2_RESET_B FlexIO1:11 GPIO4:11 USB_PHY2_TSTO_RX_HS_RXD FLEXSPI2_B_DQS
EMC_12 H1 SEMC_ADDR03 XBAR_IN24 I2C4_SCL USDHC1_WP PWM1_A3 GPIO4:12 USB_PHY1_TSTO_PLL_CLK20DIV FLEXSPI2_B_SCLK
EMC_13 A6 SEMC_ADDR04 XBAR_IN25 UART3_TX MQS_RIGHT PWM1_B3 GPIO4:13 USB_PHY2_TSTO_PLL_CLK20DIV FLEXSPI2_B_DATA00
EMC_14 B6 SEMC_ADDR05 XBAR_INOUT19 UART3_RX MQS_LEFT SPI2_CS1 GPIO4:14 USB_PHY2_TSTO_RX_SQUELCH FLEXSPI2_B_DATA01
EMC_15 B1 SEMC_ADDR06 XBAR_IN20 UART3_CTS SPDIF_OUT QTIMER3_TIMER0 GPIO4:15 USB_PHY2_TSTO_RX_DISCON_DET FLEXSPI2_B_DATA02
EMC_16 A5 SEMC_ADDR07 XBAR_IN21 UART3_RTS SPDIF_IN QTIMER3_TIMER1 GPIO4:16 FLEXSPI2_B_DATA03
EMC_17 A4 SEMC_ADDR08 PWM4_A3 UART4_CTS CAN1_TX QTIMER3_TIMER2 GPIO4:17
EMC_18 B2 SEMC_ADDR09 PWM4_B3 UART4_RTS CAN1_RX QTIMER3_TIMER3 GPIO4:18 SNVS_VIO_5_CTL
EMC_19 B4 SEMC_ADDR11 PWM2_A3 UART4_TX ENET_RX_DATA1 QTIMER2_TIMER0 GPIO4:19 SNVS_VIO_5_B
EMC_20 A3 SEMC_ADDR12 PWM2_B3 UART4_RX ENET_RX_DATA0 QTIMER2_TIMER1 GPIO4:20
EMC_21 C1 SEMC_BA0 PWM3_A3 I2C3_SDA ENET_TX_DATA1 QTIMER2_TIMER2 GPIO4:21
EMC_22 F1 SEMC_BA1 PWM3_B3 I2C3_SCL ENET_TX_DATA0 QTIMER2_TIMER3 GPIO4:22 FLEXSPI2_A_SS1_B
EMC_23 G2 SEMC_ADDR10 PWM1_A0 UART5_TX ENET_RX_EN GPT1_CAPTURE2 GPIO4:23 FLEXSPI2_A_DQS
EMC_24 D3 SEMC_CAS PWM1_B0 UART5_RX ENET_TX_EN GPT1_CAPTURE1 GPIO4:24 FLEXSPI2_A_SS0_B
EMC_25 D2 SEMC_RAS PWM1_A1 UART6_TX ENET_TX_CLK ENET_REF_CLK GPIO4:25 FLEXSPI2_A_SCLK
EMC_26 B3 SEMC_CLK PWM1_B1 UART6_RX ENET_RX_ER FlexIO1:12 GPIO4:26 FLEXSPI2_A_DATA00
EMC_27 A2 SEMC_CKE PWM1_A2 UART5_RTS SPI1_SCK FlexIO1:13 GPIO4:27 FLEXSPI2_A_DATA01
EMC_28 D1 SEMC_WE PWM1_B2 UART5_CTS SPI1_MOSI FlexIO1:14 GPIO4:28 FLEXSPI2_A_DATA02
EMC_29 E1 SEMC_CS0 PWM3_A0 UART6_RTS SPI1_MISO FlexIO1:15 GPIO4:29 FLEXSPI2_A_DATA03
EMC_30 C6 SEMC_DATA08 PWM3_B0 UART6_CTS SPI1_CS0 CSI_DATA23 GPIO4:30 ENET2_TDATA00
EMC_33 C4 SEMC_DATA11 PWM3_A2 USDHC1_RESET_B SAI3_RX_DATA CSI_DATA20 GPIO3:19 ENET2_TX_CLK ENET2_REF_CLK2
EMC_34 D4 SEMC_DATA12 PWM3_B2 USDHC1_VSELECT SAI3_RX_SYNC CSI_DATA19 GPIO3:20 ENET2_RX_ER
EMC_35 E5 SEMC_DATA13 XBAR_INOUT18 GPT1_COMPARE1 SAI3_RX_BCLK CSI_DATA18 GPIO3:21 USDHC1_CD_B ENET2_RDATA00
EMC_38 D6 SEMC_DM1 PWM1_A3 UART8_TX SAI3_TX_BCLK CSI_FIELD GPIO3:24 USDHC2_VSELECT ENET2_MDC
EMC_39 B7 SEMC_DQS PWM1_B3 UART8_RX SAI3_TX_SYNC WDOG1_B GPIO3:25 USDHC2_CD_B ENET2_MDIO SEMC_DQS4
EMC_40 A7 SEMC_RDY GPT2_CAPTURE2 SPI1_CS2 USB_OTG2_OC ENET_MDC GPIO3:26 USDHC2_RESET_B SEMC_CLK5
EMC_41 C7 SEMC_CSX0 GPT2_CAPTURE1 SPI1_CS3 USB_OTG2_PWR ENET_MDIO GPIO3:27 USDHC1_VSELECT
Name BGA ATL0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9
---- --- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
SD_B1_00 L5 USDHC2_DATA3 FLEXSPI_B_DATA3 PWM1_A3 SAI1_TX3_RX1 UART4_TX GPIO3:0 SAI3_RX_DATA
SD_B1_01 M5 USDHC2_DATA2 FLEXSPI_B_DATA2 PWM1_B3 SAI1_TX2_RX2 UART4_RX GPIO3:1 SAI3_TX_DATA
SD_B1_02 M3 USDHC2_DATA1 FLEXSPI_B_DATA1 PWM2_A3 SAI1_TX1_RX3 CAN1_TX GPIO3:2 CCM_WAIT SAI3_TX_SYNC
SD_B1_03 M4 USDHC2_DATA0 FLEXSPI_B_DATA0 PWM2_B3 SAI1_MCLK CAN1_RX GPIO3:3 CCM_PMIC_READY SAI3_TX_BCLK
SD_B1_04 P2 USDHC2_CLK FLEXSPI_B_SCLK I2C1_SCL SAI1_RX_SYNC FLEXSPI_A_SS1_B GPIO3:4 CCM_STOP SAI3_MCLK
I am considering putting an ethernet PHY chip on this board, with 6 pins/pads to connect another board having the magnetics and RJ45 connector. Or if a PHY chip isn't used, perhaps a high density connector with the RMII signals? Either way, I'm leaning towards reserving B1_04 to B1_11, and B1_14 & B1_15 for native ethernet.
Another feature I'm considering is using the bottom side for locations to add 1 or 2 QSPI memory chips, which could be either flash or psram. If that is done, pins EMC_22 to EMC_29 would likely be used. An alternative would be EMC_10 to EMC16, which supports only a single memory chip (only 1 chip select).
I know JTAG is going to come up. Let me say right now, access to JTAG signals will *not* happen for this board (if this board is even made). Please don't fill this thread with talk of JTAG debug. Yes, I know so many people have strong feelings about this. I do have long-term plans there. But this board, if it gets made, is meant to be a "quick" design that mostly leverages all the work that's gone into Teensy 4.0, to give access to pins & peripherals we couldn't get from Teensy 4.0's small form factor. That means no changes to the bootloader or programming approach. Changing any of that would almost certainly cause developing this board to drag on and on, pulling engineering time away from 1170 next year. So no JTAG.
Please remember this thread is about what pins (from this list) to bring out, and possibly what relatively small & low-risk peripheral hardware might fit nicely in the extra space we get.