Hey,
Using a teensy 4.1 I have set up a chain PIT => ADC_ETC => DMA. My problem is, that I only get one ADC_ETC trigger with four PIT-Triggers. This is independent from the speed. It stays the same if I slow down / speed up the PIT frequency. I wonder why this is the case? Is this an internal limitation?
I took a look at the Clock Tree and if I understand that correctly indeed the clock of the ADC_ETC is 1/4 of the PIT frequency.
Do I interpret this diagram correct?
Any help is appreciated!
Thanks,
Chris
Using a teensy 4.1 I have set up a chain PIT => ADC_ETC => DMA. My problem is, that I only get one ADC_ETC trigger with four PIT-Triggers. This is independent from the speed. It stays the same if I slow down / speed up the PIT frequency. I wonder why this is the case? Is this an internal limitation?
I took a look at the Clock Tree and if I understand that correctly indeed the clock of the ADC_ETC is 1/4 of the PIT frequency.
Do I interpret this diagram correct?
Any help is appreciated!
Thanks,
Chris