Well, most of the day was trying to scratch my way through a cinderblock wall with LC. I continued reading the datasheet and...... who said the SPI bus was 12MHz? Remember you made me switch to SPI0 because you had problems? and then when I started having problems, we all went nuts?
I added the notes to the new slave update.
It turns out, SPI0 slave is calculated by bus speed (24MHz) divided by 4 which is 6MHz. SPI1 is calculated by SYStem clock, which is 48MHz/4 == 12MHz
From the datasheet:
You can check the slave timings & info in the NXP datasheet:
https://www.nxp.com/docs/en/data-sheet/KL26P64M48SF5.pdf
Table 33 and 34 of page 40: "SPI slave mode timing"
It turns out, SPI0 slave is calculated by bus speed (24MHz) divided by 4 which is 6MHz. SPI1 is calculated by SYStem clock, which is 48MHz/4 == 12MHz
Code:
[ATTACH]13853._xfImport[/ATTACH]
From the datasheet:
3.9.2.1
SPI instantiation information
The number of SPI modules on this device is: two
The supported data length is: 16-bit
SPI1 includes a 4-deep FIFO of 16-bit entries.
SPI0 is clocked on the bus clock. That is, the SPI0 module clock is connected to the chip-
level bus clock.
SPI1 is clocked from the system clock. That is, the SPI1 module clock is connected to the
chip-level system clock. SPI1 is therefore disabled in Partial Stop Mode.
The SPI supports DMA request and can operate in VLPS mode. When the SPI is
operating in VLPS mode, it will operate as a slave.
SPI can wake the MCU from VLPS mode upon reception of SPI data in slave mode.
You can check the slave timings & info in the NXP datasheet:
https://www.nxp.com/docs/en/data-sheet/KL26P64M48SF5.pdf
Table 33 and 34 of page 40: "SPI slave mode timing"