defragster
Senior Member+
Nice! Good work Tony 
C:\Users\furys\AppData\Local\Temp\arduino_modified_sketch_764008\master.ino Feb 15 2019 17:51:58
F_CPU 180000000
DBG: [S_CS 15] CB Capacity: 8 Length: 250
F&F (OT=0)micros() _time==99991
F&F (OT=1)micros() _time==99992
F&F (OT=2)micros() _time==99992
F&F (OT=3)micros() _time==99992
F&F (OT=4)micros() _time==99992
F&F (OT=5)micros() _time==99992
F&F (OT=6)micros() _time==99992
F&F (OT=7)micros() _time==99992
F&F (OT=8)micros() _time==99991
F&F (OT=9)micros() _time==99991
F&F (OT=10)micros() _time==99991
F&F (OT=11)micros() _time==99991
Teensy Online @ millis=5300
D:\Users\rmartin\Documents\Arduino\libraries\SPI_MSTransfer\examples\SPI2WayExamples\slave\slave.ino Feb 15 2019 17:58:10
F_CPU 180000000
slave pins used should be 2, 11, 12, and 14 for T3.x models
the config file is for the master selected spi pins, the slave’s is fixed
Thank you for your time. I see, so no easy way to make this work... Your lib looks great though. I now know where to look if I happen come across a fitting use case for your lib.It’s won’t work because of chip specific registers and custom protocol for two way communication, a complete code rewrite is needed for the rasp pi, to be compatible with this, and it won’t be an easy task to achieve![]()
I hope this question isn't too off-topic, but this thread likely is inhabited by people who know the answer (eg tonton81).
I gather that the connections between Teensy's needs to be MISO -> MOSI and MOSI -> MISO. This is like a UART hookup rather than the way SPI is intended to be used, right?
...
Slave's wiring:
T_3.5 :: T_3.6 > Connections
GND :: GND > GND
14 :: 14 > SCK
12 :: 11 > MOSI
11 :: 12 > MISO
02 :: 15 > CS
Pin 2 was chosen so that later on when I add Serial2 support pin10 would be available. Pin 14 for clock so that Led could be used
NOTE: SPI communication between teensy master&slave, MISO GOES TO MOSI, and MOSI to MISO, crossed, just like uart.
There is an exception with LC in slave mode, it is the opposite when connected to a T3/T4. LC in slave mode, MOSI is MISO and MISO is MOSI. Basically they reversed it in slave mode.
p#1839 noted a T_3.6 - no note on T_LC.
The Master In Slave Out and Master Out Slave In follows the expected pattern as defined - the T_LC is an exception where it would not work otherwise because of the nature of the T_LC hardware as tonton81 found it in Slave mode the names are reversed when used. For normal SPI use otherwise the hardware works with the names and function as indicated on the published Teensy cards.
They could perhaps be called SPI Out and SPI In, or something like that, which is not conventional but at least correct.
void SPI_MSTransfer::begin() {
if ( _slave_access ) {
void spi0_isr(void) {
while ( !(GPIOD_PDIR & 0x01) ) {
if ( SPI0_SR & 0xF0 ) {
SPI0_PUSHR_SLAVE = 0xDEAF; data[buffer_pos] = SPI0_POPR; buffer_pos++;
if ( buffer_pos >= SPI_MST_DATA_BUFFER_MAX ) break; // BUFFER LENGTH PROTECTION
}
if ( data[1] && buffer_pos >= data[1] ) break;
}
while ( !(GPIOD_PDIR & 0x01) ) { // wait here until MASTER confirms F&F receipt
if ( SPI0_SR & 0xF0 ) {
SPI0_PUSHR_SLAVE = 0xBABE;
if ( SPI0_POPR == 0xD0D0 ) break;
}
}
SPI0_SR |= SPI_SR_RFDF; return;