Project: SPI_MSTransfer

tonton81 · Mar 5, 2022

exactly, now add a jumper from GND (between 3.3V and 5V pin) to other T4, you'll constantly get only millis() if there is a conection issue, otherwise you'll start seeing data asap

KurtE · Mar 5, 2022

You are right that it appears to need both grounds hooked up... Not sure what that is telling us...

tonton81 · Mar 5, 2022

KurtE said:
You are right that it appears to need both grounds hooked up... Not sure what that is telling us...

so you got it working?
T3/LC doesn't need that extra ground

mjs513 · Mar 5, 2022

Ok Just completely redid my setup and used my new breakout board:

EDIT: NOTE This is with a T4.1 as master and T4 as slave

and now its working with the second jumper added:

Code:

millis: 605034
BEEF F7 F8 F9 DEAD  --> Length: 5 --> PacketID: 430E
millis: 606035
BEEF F7 F8 F9 DEAD  --> Length: 5 --> PacketID: 5F34
millis: 607036
BEEF F7 F8 F9 DEAD  --> Length: 5 --> PacketID: 5D28
millis: 608037
BEEF F7 F8 F9 DEAD  --> Length: 5 --> PacketID: 6D91
millis: 609038
BEEF F7 F8 F9 DEAD  --> Length: 5 --> PacketID: 7AE8
millis: 610039
BEEF F7 F8 F9 DEAD  --> Length: 5 --> PacketID: 61B9
millis: 611040
BEEF F7 F8 F9 DEAD  --> Length: 5 --> PacketID: 4DAD
millis: 612041
BEEF F7 F8 F9 DEAD  --> Length: 5 --> PacketID: 760F
millis: 613042

Master

Code:

643156
State: 0

  Detected slaves: 
    Slave 1 --> ID: 0x1234
    Mode: Standalone

As Kurt said - not sure why its needed or >>>

tonton81 · Mar 5, 2022

It also works if I take the GND pin between 3.3V and 5V pins on T4 master and connect it next to pin 0 of the slave (not using the GND pin on slave's mid 3.3V/5V area). It also works if I use the master's GND (3.3v/5V pin area) to the USB shield of the slave...

mjs513 · Mar 5, 2022

Well - mine is now working if I just connect the GND near pin 0 to the GND on the breakout board I am using - I swapped ground wire and no need for the second ground wire.

EDIT: Just check the PCB design and turns out that my breakout board has the 2 grounds connected

Got lucky

defragster · Mar 5, 2022

@KurtE - connect the second GND [between VIN & 3.3V] as noted above by Tony - any diff?

KurtE · Mar 5, 2022

defragster said:
@KurtE - connect the second GND [between VIN & 3.3V] as noted above by Tony - any diff?

Yes (noted in 1902) that it appeared to need both grounds

mjs513 · Mar 5, 2022

@tonton81 - @KurtE
Here is another strange situation. I put the T4.1 as master and the T4 as slave in the setup in post #1889. Notice anything strange:
View attachment 27749

tonton81 · Mar 5, 2022

mjs513 said:
@tonton81 - @KurtE
Here is another strange situation. I put the T4.1 as master and the T4 as slave in the setup in post #1889. Notice anything strange:
View attachment 27749

yes, your attachments never work

mjs513 · Mar 5, 2022

tonton81 said:
yes, your attachments never work

YEah - don;t know why

mjs513 · Mar 5, 2022

Lets see if this works

Only works if I go to the advanced menu - not sure what happened

EDIT: The problem as some playing with is with grounds are good with the wires I am using on the this setup because now I how the T4-T4 setup working

defragster · Mar 5, 2022

KurtE said:
Yes (noted in 1902) that it appeared to need both grounds

Just checking, as the pic didn't show that wire.

KurtE · Mar 5, 2022

And for another strangeness if I hook up the Logic Analyzer, to the double ground one, it stops working again...

This time I put on both analog and digital capture:

mjs513 · Mar 5, 2022

KurtE said:
And for another strangeness if I hook up the Logic Analyzer, to the double ground one, it stops working again...

This time I put on both analog and digital capture:

View attachment 27751

Ok no idea whats going on! Strangeness abounds

KurtE · Mar 5, 2022

So far I am wondering how the Slave SPIO pins are configured.

I know that there is:

Code:

    IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 0x3; /* LPSPI4 SCK (CLK) */
    IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 0x3; /* LPSPI4 SDI (MISO) */
    IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 0x3; /* LPSPI4 SDO (MOSI) */
    IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 0x3; /* LPSPI4 PCS0 (CS) */

But wondering where the ones like:

Code:

IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03

Wondering in both cases both master and slave if we need to setup drive strength and speed.

Also wondering if things like MISO on the slave if it needs to be configured like Open Drain...

tonton81 · Mar 5, 2022

SLAVE_PINS_ADDR;
spiAddr[0] = 0; /* PCS0_SELECT_INPUT */
spiAddr[1] = 0; /* SCK_SELECT_INPUT */
spiAddr[2] = 0; /* SDI_SELECT_INPUT */
spiAddr[3] = 0; /* SDO_SELECT_INPUT */
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 0x3; /* LPSPI4 SCK (CLK) */
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 0x3; /* LPSPI4 SDI (MISO) */
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 0x3; /* LPSPI4 SDO (MOSI) */
IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 0x3; /* LPSPI4 PCS0 (CS) */

sorry im using defines in case we add other busses later, since they follow same offsets. if you want to play with the pad settings of the slave just put additional stuff under those lines for pins 10-13

in the above lines, only the daisy register is set and the MUX register

tonton81 · Mar 5, 2022

you can try adding this found on another thread if you want to play with those settings:

Code:

    uint32_t fastio = IOMUXC_PAD_DSE(6) | IOMUXC_PAD_SPEED(1);
    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = fastio;
    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = fastio;
    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = fastio;

KurtE · Mar 5, 2022

Again the ones like:

Code:

IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 0x3; /* LPSPI4 SDO (MOSI) */

Sets the Pin to SPI mode...

But it does not set the other pin/port register that controls things like drive speed, PULL UP/Down...
That in this case would be:

Code:

IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02

In the SPI library we set them up like:

Code:

	uint32_t fastio = IOMUXC_PAD_DSE(7) | IOMUXC_PAD_SPEED(2);
	//uint32_t fastio = IOMUXC_PAD_DSE(6) | IOMUXC_PAD_SPEED(1);
	//uint32_t fastio = IOMUXC_PAD_DSE(3) | IOMUXC_PAD_SPEED(3);
	//Serial.printf("SPI MISO: %d MOSI: %d, SCK: %d\n", hardware().miso_pin[miso_pin_index], hardware().mosi_pin[mosi_pin_index], hardware().sck_pin[sck_pin_index]);
	*(portControlRegister(hardware().miso_pin[miso_pin_index])) = fastio;
	*(portControlRegister(hardware().mosi_pin[mosi_pin_index])) = fastio;
	*(portControlRegister(hardware().sck_pin[sck_pin_index])) = fastio;

I still at times wonder what the best settings should be

tonton81 · Mar 5, 2022

this seems to work, using DSE higher than 4 cripples it, setting no DSE works, only setting the pin speed was sufficient, seems to run without the extra jumper now

Code:

    uint32_t fastio = IOMUXC_PAD_SPEED(3);
    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = fastio;
    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = fastio;
    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = fastio;

EDIT, nevermind, although it works slavedetection stopped working lol
i set DSE to 3

any testers?

Code:

    uint32_t fastio = IOMUXC_PAD_DSE(3) | IOMUXC_PAD_SPEED(3);
    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = fastio;
    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = fastio;
    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = fastio;

tonton81 · Mar 5, 2022

here is the updated patch, red lines need to be added for testing

Code:

SPI_MSTransfer_T4_FUNC SPI_MSTransfer_T4_OPT::SPI_MSTransfer_T4() {
  if ( port == &SPI ) {
    _LPSPI4 = this;
    _portnum = 3;
    CCM_CCGR1 |= (3UL << 6);
    nvic_irq = 32 + _portnum;
    _VectorsRam[16 + nvic_irq] = lpspi4_slave_isr;

    /* Alternate pins not broken out on Teensy 4.0/4.1 for LPSPI4 */
    SLAVE_PINS_ADDR;
    spiAddr[0] = 0; /* PCS0_SELECT_INPUT */
    spiAddr[1] = 0; /* SCK_SELECT_INPUT */
    spiAddr[2] = 0; /* SDI_SELECT_INPUT */
    spiAddr[3] = 0; /* SDO_SELECT_INPUT */
    IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 0x3; /* LPSPI4 SCK (CLK) */
    IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 0x3; /* LPSPI4 SDI (MISO) */
    IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 0x3; /* LPSPI4 SDO (MOSI) */
    IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 0x3; /* LPSPI4 PCS0 (CS) */
[COLOR="#FF0000"]    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = IOMUXC_PAD_DSE(3) | IOMUXC_PAD_SPEED(3);
    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = IOMUXC_PAD_DSE(3) | IOMUXC_PAD_SPEED(3);
    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = IOMUXC_PAD_DSE(3) | IOMUXC_PAD_SPEED(3);[/COLOR]
  } 
}

mjs513 · Mar 5, 2022

tonton81 said:

here is the updated patch, red lines need to be added for testing

Code:

SPI_MSTransfer_T4_FUNC SPI_MSTransfer_T4_OPT::SPI_MSTransfer_T4() {
  if ( port == &SPI ) {
    _LPSPI4 = this;
    _portnum = 3;
    CCM_CCGR1 |= (3UL << 6);
    nvic_irq = 32 + _portnum;
    _VectorsRam[16 + nvic_irq] = lpspi4_slave_isr;

    /* Alternate pins not broken out on Teensy 4.0/4.1 for LPSPI4 */
    SLAVE_PINS_ADDR;
    spiAddr[0] = 0; /* PCS0_SELECT_INPUT */
    spiAddr[1] = 0; /* SCK_SELECT_INPUT */
    spiAddr[2] = 0; /* SDI_SELECT_INPUT */
    spiAddr[3] = 0; /* SDO_SELECT_INPUT */
    IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 0x3; /* LPSPI4 SCK (CLK) */
    IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 0x3; /* LPSPI4 SDI (MISO) */
    IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 0x3; /* LPSPI4 SDO (MOSI) */
    IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 0x3; /* LPSPI4 PCS0 (CS) */
[COLOR="#FF0000"]    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = IOMUXC_PAD_DSE(3) | IOMUXC_PAD_SPEED(3);
    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = IOMUXC_PAD_DSE(3) | IOMUXC_PAD_SPEED(3);
    IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = IOMUXC_PAD_DSE(3) | IOMUXC_PAD_SPEED(3);[/COLOR]
  } 
}

Sorry was having dinner - just tried it but still needed the 2 gnds connected. Changing it SPI.cpp now to see what happens when you have both configured with the same DSEs and speeds

mjs513 · Mar 5, 2022

@tonton81 - @KurtE

Just changed he fastio in SPI.cpp for the 1062 (line 1286) to

Code:

	uint32_t fastio = IOMUXC_PAD_DSE(3) | IOMUXC_PAD_SPEED(3);

I have the 2 T4s working with only the GND pin near pin 0 connected between the 2 T4's

tonton81 · Mar 5, 2022

so it is SPI library issue? makes sense a bit since T3/LC works without additional ground?

EDIT, nope, doesn't work without the additional ground.
With the patched 3 lines it slave in works without the ground

mike, you said the grounds were joined on your board

mjs513 · Mar 6, 2022

tonton81 said:
so it is SPI library issue? makes sense a bit since T3/LC works without additional ground?

EDIT, nope, doesn't work without the additional ground.
With the patched 3 lines it slave in works without the ground

mike, you said the grounds were joined on your board

Morning Tony,

Went back to my original setup with 2 T4's as shown in post 1889.

A couple of things.
1. Found that you have to reload Master as well as Slave when you change DSE in SPI.cpp then it works without the extra ground. Also was able to transfer every 5 ms without issue.
2. If I changed the DSE just in SPI_MStranfer_t4.tpp it seems to be hit or miss. When I configured SPI.cpp back to the original settings and added the extra DSE lines in the tpp it worked with the one ground. But when I changed the master to test at a faster it failed to work without the extra ground.

So my thought is that both the master and slave need the changes to DSE to work consistently

Project: SPI_MSTransfer

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