Purpose of the R5 resistor - Teensy 4.0

Hi,

I'm trying to get a better understanding of the teensy 4.0 but I'm really struggling to understand what the purpose of the R5 resistor is? From all the information I could find online about these everything seems to suggest it should not be configured the way it is by being connected to ground? I got so desperate I used ChatGPT and even it told me the same thing.

From what I understand, it should be a bias/feedback resistor but that should be connected via the crystals poles no? Instead it seems to go to ground? (Maybe I'm just an idiot and am reading the schematic wrong). I've attached the schematic drawing with the area I have mentioned as well as the link to the page with the schematic.

Any help appreciated. Rude and unhelpful comments will be ignored.
Thanks.



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Probably only a few engineers deep within NXP know the real reason. The best any of us can do is guess.

An oscillator circuit using only a single stage inverter gate (only 2 transistors) usually needs 2 resistors, one in series with the output to limit the drive current, and a feedback resistor between the output to input which establishes the DC input voltage that ends up at the point where both N and P channel transistors are partially conducting so it acts like a linear amplifier rather than a digital gate.

My guess is they had a previously designed crystal oscillator designed circuit from some other chip, which somehow achieves that high impedance feedback with a rather crafty design. Like pretty much all CMOS circuitry, whatever feedback or other input bias circuitry they used almost certainly depends on transistors having certain ratio of channel width. RT1052 and RT1062 were the first IMXRT chips they made. That prior circuit was probably well tested with some other silicon process, maybe 90mn or 65mn. When they implemented it in the 40nm process used for IMXRT, maybe the ratio of N vs P channel transconductance turned out to be different (perhaps N-channel not quite as strong relative to P as with older silicon) which threw off the transistor size ratio carefully planned for other silicon process, and the amplifier's DC input voltage ended up off slightly? Maybe...

But I don't really know. Probably nobody outside 1 specific team in NXP knows why. Best we can do is guess, and of course follow their guidance that must have come from those folks inside NXP who do actually know.
 
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