Question about FlexIO bidirectional output data and bidirectional output enable interaction

[DrItanium]

I'm trying to emulate a simple EBI/SMI interface using FlexIO3 on a teensy 4.1 so I can offload the timing requirements of communicating with two CH351 in 32-bit io expander mode (It uses a simple parallel bus design). I am doing this so I can interface the address and data bus of an Intel i960SB-16/10 (running at 12MHz). One CH351 is used to read in the 32 address lines that the i960 provides. The other CH351 is used to access the 16-bit data bus in a dual 16-bit data bus configuration (the PCBs I've made actually split the 16-bit data bus off into two "pipes" of a fixed direction for me) where one set of 16-bits is read only and other set of 16-bits is in a write only configuration. On the teensy side, I use the following layout for interfacing with the simple parallel bus (https://github.com/DrItanium/SxChip...0e76580e01d/projects/Chipset/include/Pinout.h):

- ADR0 (Pin 19) | FlexIO3.0
- ADR1 (Pin 18) | FlexIO3.1
- ADR2 (Pin 14) | FlexIO3.2
- ADR3 (Pin 15) | FlexIO3.3
- ADR4 (Pin 40) | FlexIO3.4
- ADR5 (Pin 41) | FlexIO3.5
- ~RD (Pin 17) | FlexIO3.6
- ~WR (Pin 16) | FlexIO3.7
- D0 (Pin 22) | FlexIO3.8
- D1 (Pin 23) | FlexIO3.9
- D2 (Pin 20) | FlexIO3.10
- D3 (Pin 21) | FlexIO3.11
- D4 (Pin 38) | FlexIO3.12
- D5 (Pin 39) | FlexIO3.13
- D6 (Pin 26) | FlexIO3.14
- D7 (Pin 27) | FlexIO3.15

Currently, I am using the Cortex-M7 to time out accesses to the EBI and it working quite well (I am using direct port accesses to do this). In an effort to increase performance further I am trying to figure out how to migrate aspects of this over to FlexIO3 but I am hitting some confusion when dealing with the bidirectional 8-bit data port. I am reading in the Reference Manual that one can configure a shifter or timer to act as bidirectional output enable (PINCFG = 0b01) to control pins that are configured as bidirectional output data (PINCFG = 0b10). However, I cannot find any reference how to _connect_ them together and the diagram for the shifter microarchitecture does not show this interaction either. In fact, nothing else in the manual actually describes how one "connects" these together.

The more I read this, the more it seems that the FlexIO hardware automatically connects these two aspects automatically once configured. Is this a correct assumption?

If this assumption is correct, then does that mean the following theoretical configuration will just work (forgive the slightly abstract nature):

- FlexIO3.Shifter0: Parallel Transmit (8 bit) in Bidirectional output data PINCFG "mode" using FlexIO3 pins [15:8]
- FlexIO3.Shifter1: Transmit (1 bit) in bidirectional output enable PINCFG "mode" (I want the processor to be able to control the direction internally)
- FlexIO3.Shifter4: Parallel Receive (8 bit) in bidirectional output data PINCFG "mode" using FlexIO3 pins [15:8]

The magic aspect of this is really confusing me...

 

[jmarsh]

- FlexIO3.Shifter4: Parallel Receive (8 bit) in bidirectional output data PINCFG "mode" using FlexIO3 pins [15:8]

If it's a receiver it should use input mode.
Shifter 1 will have to use 8-bit width in order to control direction of all 8 lines.

I would consider changing your pin definitions so the data pins are on FlexIO 0-7, so their direction can be controlled by state mode shifters.

 

[DrItanium]

If it's a receiver it should use input mode.
Shifter 1 will have to use 8-bit width in order to control direction of all 8 lines.

I would consider changing your pin definitions so the data pins are on FlexIO 0-7, so their direction can be controlled by state mode shifters.

That is really helpful thanks .

I can't change those pin definitions right now without redesigning the interface PCB but I will make a note to do that when I go to make a new spin of the interface PCB.

I am assuming that you would configure the state machine in question be in "bidirectional output enable" PINCFG "mode" ?

 

[jmarsh]

I am assuming that you would configure the state machine in question be in "bidirectional output enable" PINCFG "mode" ?

Yes.
The main problem is there's only a couple of shifters that can do parallel output to IOs (width >1) so using state mode is almost always necessary if you want to use both bidrectional output data and bidirection output enable.

 

[DrItanium]

Ah, I see. So it really is smart to rearrange the data lines to be the lowest 8 flexio pins. I will put this on hold for now and redesign the interface PCB first. Thank you!