Questions about analogWriteFrequency()

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DiamondDrake

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I am looking to produce a few clock signals with the teensy, I've found in the forums you can change the base frequency of the PWM by manipulating the timers and then use them to generate signals. The analogWriteFrequency() function does the math for you and sets the prescaler and divisor for the timer related to that pin.

But in a few places I've seen Paul remark about "then you can't get a 50% duty cycle" or something to that nature.

If my goal is a 3.3v square wave clock coming from pin 3 at 11 mhz,
I would use analogWriteFrequency(3, 11000000);
but for bet results what would I want to set the analog resolution to? 8 bits? and then analogWrite(3, 128)?
I realize the analog write resolution is just a scalar that is handled in code, but the question is remains what is the duty cycle you want to write to the analog pin when using it as a clock, if you can't reach 50% with high frequencies?

Or is there some formula for target dutycycle when trying to generate clocks with PWM?


relevant sources:
Similar question not fully explained
Teensy Core on github with analogWriteFrequency

I can just play around with a scope and see what works, but I was hoping for a definitive "you SHOULD do it this way" statement from someone with a little more experience dealing with clocks and hardware timers.
 
defragster said:
Does the table here help?: https://www.pjrc.com/teensy/td_pulse.html

Faster speed requires lower bit resolution - at highest speed you only get 1 bit - on/off and 50% duty cycle as I understand what Paul wrote recently.
Click to expand...

I saw the chart but I don't know that it clearly answers the question. So to get up to 12mhz you need to set the resolution to 4 bits? I thought the resolution was just a mask for the accuracy it doesn't actually change any settings.
What should you analogwrite to get the frequency you want? 50%?
 
PaulStoffregen said:
Thanks, that works well. Can you use this same technique to create a 16mhz clock?
Click to expand...
Yes, since the peripheral clock is 48 MHz when the CPU runs at 48 or 96 MHz, but you can't get a 50% duty cycle.
Click to expand...
DiamondDrake said:
But in a few places I've seen Paul remark about "then you can't get a 50% duty cycle" or something to that nature.
Click to expand...
The timer counter counts at 48MHz. So to do 16MHz, it needs to count from 0 to 2 (and then wrap). That means you can get a duty cycle that's either 1/3 or 2/3.

You can't do 11MHz, the closest you get with the default bus clocks is 48MHz / 4 = 12MHz (timer counter will count from 0 to 3) or 48MHz / 5 = 9.6MHz (timer counter will count from 0 to 4).
 
I see now, only integer divisions of the reference clock, and you would usually want a 50% duty cycle, but really all that matters is distance between positive clocking edges.

thank you
 
If you clock Teensy 3.6 at 168 MHz, F_BUS is 56 MHz. That would let you 11.2 MHz.

But since the division is by 5 (an odd number) you can't get 50% duty cycle.

Or if you overclock F_BUS to 120 MHz (which is double its rated maximum), you could get 10.909 MHz. Again, not 50%...
 
PaulStoffregen said:
If you clock Teensy 3.6 at 168 MHz, F_BUS is 56 MHz. That would let you 11.2 MHz.

But since the division is by 5 (an odd number) you can't get 50% duty cycle.

Or if you overclock F_BUS to 120 MHz (which is double its rated maximum), you could get 10.909 MHz. Again, not 50%...
Click to expand...

Thank you Paul,

I think I can get away with generating 8 or 12 mhz.

My take away from this thread cliffnotes version:
To use PWM for generating a clock signal, the solid clock options are finding values that are an an even integer division of the peripheral clock (48mhz on teens 3.2/ 56mhz on teensy 3.6) and enable it with a 50% duty cycle.

Here's the 100 fastest clocks you can generate 50% duty cycles for using the PWM timers on the teensy 3.2
Code: 
Clock Speed : 48000000 Hz (      48 MHz), Divisor 1
Clock Speed : 24000000 Hz (      24 MHz), Divisor 2
Clock Speed : 12000000 Hz (      12 MHz), Divisor 4
Clock Speed :  8000000 Hz (       8 MHz), Divisor 6
Clock Speed :  6000000 Hz (       6 MHz), Divisor 8
Clock Speed :  4800000 Hz (     4.8 MHz), Divisor 10
Clock Speed :  4000000 Hz (       4 MHz), Divisor 12
Clock Speed :  3428571 Hz (3.428571 MHz), Divisor 14
Clock Speed :  3000000 Hz (       3 MHz), Divisor 16
Clock Speed :  2666666 Hz (2.666667 MHz), Divisor 18
Clock Speed :  2400000 Hz (     2.4 MHz), Divisor 20
Clock Speed :  2181818 Hz (2.181818 MHz), Divisor 22
Clock Speed :  2000000 Hz (       2 MHz), Divisor 24
Clock Speed :  1846153 Hz (1.846154 MHz), Divisor 26
Clock Speed :  1714285 Hz (1.714286 MHz), Divisor 28
Clock Speed :  1600000 Hz (     1.6 MHz), Divisor 30
Clock Speed :  1500000 Hz (     1.5 MHz), Divisor 32
Clock Speed :  1411764 Hz (1.411765 MHz), Divisor 34
Clock Speed :  1333333 Hz (1.333333 MHz), Divisor 36
Clock Speed :  1263157 Hz (1.263158 MHz), Divisor 38
Clock Speed :  1200000 Hz (     1.2 MHz), Divisor 40
Clock Speed :  1142857 Hz (1.142857 MHz), Divisor 42
Clock Speed :  1090909 Hz (1.090909 MHz), Divisor 44
Clock Speed :  1043478 Hz (1.043478 MHz), Divisor 46
Clock Speed :  1000000 Hz (      10 KHz), Divisor 48
Clock Speed :   960000 Hz (     9.6 KHz), Divisor 50
Clock Speed :   923076 Hz (9.230769 KHz), Divisor 52
Clock Speed :   888888 Hz (8.888888 KHz), Divisor 54
Clock Speed :   857142 Hz (8.571428 KHz), Divisor 56
Clock Speed :   827586 Hz (8.275862 KHz), Divisor 58
Clock Speed :   800000 Hz (       8 KHz), Divisor 60
Clock Speed :   774193 Hz (7.741936 KHz), Divisor 62
Clock Speed :   750000 Hz (     7.5 KHz), Divisor 64
Clock Speed :   727272 Hz (7.272727 KHz), Divisor 66
Clock Speed :   705882 Hz (7.058824 KHz), Divisor 68
Clock Speed :   685714 Hz (6.857143 KHz), Divisor 70
Clock Speed :   666666 Hz (6.666667 KHz), Divisor 72
Clock Speed :   648648 Hz (6.486486 KHz), Divisor 74
Clock Speed :   631578 Hz (6.315789 KHz), Divisor 76
Clock Speed :   615384 Hz (6.153846 KHz), Divisor 78
Clock Speed :   600000 Hz (       6 KHz), Divisor 80
Clock Speed :   585365 Hz (5.853659 KHz), Divisor 82
Clock Speed :   571428 Hz (5.714286 KHz), Divisor 84
Clock Speed :   558139 Hz (5.581396 KHz), Divisor 86
Clock Speed :   545454 Hz (5.454545 KHz), Divisor 88
Clock Speed :   533333 Hz (5.333333 KHz), Divisor 90
Clock Speed :   521739 Hz (5.217391 KHz), Divisor 92
Clock Speed :   510638 Hz (5.106383 KHz), Divisor 94
Clock Speed :   500000 Hz (       5 KHz), Divisor 96
Clock Speed :   489795 Hz (4.897959 KHz), Divisor 98
Clock Speed :   480000 Hz (     4.8 KHz), Divisor 100
Clock Speed :   470588 Hz (4.705883 KHz), Divisor 102
Clock Speed :   461538 Hz (4.615385 KHz), Divisor 104
Clock Speed :   452830 Hz (4.528302 KHz), Divisor 106
Clock Speed :   444444 Hz (4.444444 KHz), Divisor 108
Clock Speed :   436363 Hz (4.363636 KHz), Divisor 110
Clock Speed :   428571 Hz (4.285714 KHz), Divisor 112
Clock Speed :   421052 Hz (4.210526 KHz), Divisor 114
Clock Speed :   413793 Hz (4.137931 KHz), Divisor 116
Clock Speed :   406779 Hz (4.067797 KHz), Divisor 118
Clock Speed :   400000 Hz (       4 KHz), Divisor 120
Clock Speed :   393442 Hz (3.934426 KHz), Divisor 122
Clock Speed :   387096 Hz (3.870968 KHz), Divisor 124
Clock Speed :   380952 Hz (3.809524 KHz), Divisor 126
Clock Speed :   375000 Hz (    3.75 KHz), Divisor 128
Clock Speed :   369230 Hz (3.692308 KHz), Divisor 130
Clock Speed :   363636 Hz (3.636364 KHz), Divisor 132
Clock Speed :   358208 Hz ( 3.58209 KHz), Divisor 134
Clock Speed :   352941 Hz (3.529412 KHz), Divisor 136
Clock Speed :   347826 Hz (3.478261 KHz), Divisor 138
Clock Speed :   342857 Hz (3.428571 KHz), Divisor 140
Clock Speed :   338028 Hz (3.380281 KHz), Divisor 142
Clock Speed :   333333 Hz (3.333333 KHz), Divisor 144
Clock Speed :   328767 Hz (3.287671 KHz), Divisor 146
Clock Speed :   324324 Hz (3.243243 KHz), Divisor 148
Clock Speed :   320000 Hz (     3.2 KHz), Divisor 150
Clock Speed :   315789 Hz (3.157895 KHz), Divisor 152
Clock Speed :   311688 Hz (3.116883 KHz), Divisor 154
Clock Speed :   307692 Hz (3.076923 KHz), Divisor 156
Clock Speed :   303797 Hz (3.037975 KHz), Divisor 158
Clock Speed :   300000 Hz (       3 KHz), Divisor 160
Clock Speed :   296296 Hz (2.962963 KHz), Divisor 162
Clock Speed :   292682 Hz (2.926829 KHz), Divisor 164
Clock Speed :   289156 Hz (2.891566 KHz), Divisor 166
Clock Speed :   285714 Hz (2.857143 KHz), Divisor 168
Clock Speed :   282352 Hz (2.823529 KHz), Divisor 170
Clock Speed :   279069 Hz (2.790698 KHz), Divisor 172
Clock Speed :   275862 Hz (2.758621 KHz), Divisor 174
Clock Speed :   272727 Hz (2.727273 KHz), Divisor 176
Clock Speed :   269662 Hz (2.696629 KHz), Divisor 178
Clock Speed :   266666 Hz (2.666667 KHz), Divisor 180
Clock Speed :   263736 Hz (2.637362 KHz), Divisor 182
Clock Speed :   260869 Hz (2.608696 KHz), Divisor 184
Clock Speed :   258064 Hz (2.580645 KHz), Divisor 186
Clock Speed :   255319 Hz (2.553192 KHz), Divisor 188
Clock Speed :   252631 Hz (2.526316 KHz), Divisor 190
Clock Speed :   250000 Hz (     2.5 KHz), Divisor 192
Clock Speed :   247422 Hz (2.474227 KHz), Divisor 194
Clock Speed :   244897 Hz ( 2.44898 KHz), Divisor 196
Clock Speed :   242424 Hz (2.424242 KHz), Divisor 198

Do I have this more or less correct?
 
Yes, except dividing by 1 doesn't allow any duty cycle other than 0 or 100%.

Other F_BUS options are available, like 36 or 60 MHz. See kinetis.h.
 
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