RAM1 padding

[CollinK]

I did search but I can't find a good answer to this:

Why does RAM1 get allocated in like 32k chunks? I hate wasting memory for seemingly no reason. I'm sure there is one but I don't know it. If I have like 25k of padding, WHY? Why can't the gap between things be on like 16 byte boundaries or something? Is there a technical hardware reason (I would guess yes?) that aligning to 32k is somehow better even though it's wasteful? It's very deflating to try to free up memory only to see it all go to padding instead of being useful.

 

[jmarsh]

Each bank can be allocated in 4 ways: unallocated, ITCM (code memory), DTCM (data memory) or OCRAM (extra RAM2). Four possible values requires two bits of storage.
The way this is handled in the hardware is by dividing a single 32-bit register (IOMUXC_GPR_GPR17) into 2-bit fields, allowing for 16 total banks. 512KB divided by 16 = each bank is 32KB.

 

[PaulStoffregen]

Why does RAM1 get allocated in like 32k chunks?

It's a hardware limitation. Here's the info from the hardware reference manual.

Why can't the gap between things be on like 16 byte boundaries or something? Is there a technical hardware reason (I would guess yes?) that aligning to 32k is somehow better even though it's wasteful?

Only engineers at NXP who designed the hardware could give a definitive answer.

But we can guess and speculate about some of the trade-offs and choices they likely faced. The Cortex-M7's ITCM and DTCM buses are 64 bits wide and run at 600 MHz. Logic circuitry between the ITCM / DTCM address lines and the actual memory array which implements the memory mapping adds delay, and mux circuitry that steers those data paths to the correct physical memory probably also adds delay. Maybe they needed to keep it fairly simple to prevent those delays from causing problems at 600 MHz memory speed?

Or it could be a case of an early decision that 32K was enough granularity and the engineers who designed the circuitry just followed a requirements document. Difficult to know what really goes on in design of these chips, but huge corporations like NXP often follow a very "top down" approach. For all we really know, maybe finer granularity could have been made but the specification may have been finalized long before anyone really did the actual implementation work?